Performance Analysis of 6T and 9T SRAM
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2019 by IJETT Journal|
|Year of Publication : 2019|
|Authors : Ezeogu Chinonso Apollos
|DOI : 10.14445/22315381/IJETT-V67I4P220|
MLA Style: Ezeogu Chinonso Apollos "Performance Analysis of 6T and 9T SRAM" International Journal of Engineering Trends and Technology 67.4 (2019): 88-102.
APA Style:Ezeogu Chinonso Apollos (2019). Performance Analysis of 6T and 9T SRAM International Journal of Engineering Trends and Technology, 67(4), 88-102.
The SRAM cell is made up of latch, which ensures that the cell data is preserved as long as power is turned on and refresh operation is not required for the SRAM cell. SRAM is widely used for on-chip cache memory in microprocessors, game software, computers, workstations, portable handheld devices due to high data speed, low power consumption, low voltage supply, no-refresh needed. Therefore, to build a reliable cache/memory, the individual cell (SRAM) must be designed to have high Static Noise Margin (SNM). In sub-threshold region, conventional 6T-cell SRAM experiences poor read and write ability, and reduction in the SNM at various fluctuation of the threshold voltage, supply voltage down scaling, and technology scaling in nano-meter ranges (180nm, 90nm, 45nm, 22nm, 16nm and 10nm). Thus, noise margin becomes worse during read and write operations compared to hold operation which the internal feedback operates independent of the access transistors. Due to these limitations of the conventional 6T SRAM cell, we have proposed a 9T SRAM that will drastically minimize these limitations; the extra three transistors added to the 6T topology will improve the read, hold and write SNM. The design and simulation results were carried out using Cadence Virtuoso to evaluate the performance of 6T and 9T SRAM cells. Keywords — SRAM, Performance Analysis,6T,9T, Stability, PVT, Leakage current, N-curve, SNM.
. Ezeogu, Apollos, “Process Variation Aware Non-Volatile (Memristive) 9T SRAM Memory Design in Nano-CMOS Technologies”, M.Sc. Theses submitted to University of Bristol, United Kingdom, Oct. 2013.
. K. Dhanumjaya, MN. Giri Prasad, K. PAdmaraju, M. Raja Reddy, “ Low Power and Improved Read Stability Cache Design in 45nm Technology”, International Journal of Engineering Research and Development eISSN : 2278-067X, pISSN : 2278-800X, www.ijerd.com Volume 2, Issue 2 (July 2012), PP. 01-07
. G. K. Reddy, Kapil Jainwal, Jawar Singh and Saraju P. Mohanty, “ Process Variation Tolerant 9T SRAM Bitcell Design”, Quality Electronic Design (ISQED), 2012 13th International Symposium on 19-21 March 2012, pp 493 - 497, Santa Clara, CA.
. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V power supply high-speed digital circuit technology with multi threshold-voltage CMOS,” IEEE J. Solid-State Circuits, Vol. 30, No. 8, pp. 847–854, 1995.
. Govind Prasad, “Design of Low Power and High Stable Proposed SRAM cell Structure”, International Journal of VLSI and Embedded Systems-IJVES ISSN: 2249 – 6556, 2013.
. Evelyn Grossar, Michele Stucchi, Karen Maex, and Wim Dehaene, “ Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies”, IEEE Journal of Solid-State Circuits, vol. 41, No.11, November 2006.
. Archna bai, “ SRAM Modelling for Read Stability and Write Ability Cell , International Journal of Emerging Technologies in Computational and Applied Sciences, 2 (1), Aug.-Nov., 2012, pp. 26-31.
. Kaushik Roy, Saibal mukhopadhyay and Maymoodi - Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Sub micrometer CMOS Circuits”, Proceedings of the IEEE, Vol. 91, No. 2, February , 2003.
. Jawar Singh, Jimson Mathew, Saraju P. Mohanty and Dhiraj K. Pradhan, “Statistical Analysis of Steady State Leakage Currents in Nano-CMOS Devices”, Published in: Norchip,19-20 Nov. 2007 pp. 1 - 4, Aalborg.
. Benton H. Calhoun and Anantha Chandrakasan, “Analyzing Static Noise Margin for Subthreshold SRAM in 65nm CMOS” Proceedings of ESSCIRC, 2005.
. H. Kim and K. Roy, “Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors,” presented at the Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. 2002.
. K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, “50% active power saving without speed degradation using stand-by power reduction (SPR) circuit,” ISSCC Dig. Tech.Papers, pp. 318–319, 1995.
. H. Kawaguchi, K. Nose, and T. Sakurai, “A CMOS scheme for 0.5V supply voltage with pico ampere standby current,”in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 1998, pp. 192–193.
. K. Dhanumjay, M. Sudha, Dr.MN.Giri Prasad, K. Padmaraju “Cell stability Analysis of Conventional 6T Dynamic 8T SRAM Cell in 45nm Technology”, “International Journal of VLSI design & Communication Systems (VLSICS), Vol. 3, No.2, pp. 41 - 51, April, 2012
. Agarwal, H. Li, and K. Roy, “DRG-Cache: A data retention gated ground cache for low power,” in Proceedings. 39th Design Automation Conference, 2002, pp. 473–478.
. Mutyam M, Narayanan V. “Working with Process Variation Aware Cache”. Design, Automation & Test in Europe Conference & Exhibition p1-6, 2007.
SRAM, Performance Analysis,6T,9T, Stability, PVT, Leakage current, N-curve, SNM.