Green and Sustainable FPGA Based Counter For IOT Based Processor
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2019 by IJETT Journal|
|Year of Publication : 2019|
|Authors : Sandhya, Nidhi B.Satija, Priyank Singhal
|DOI : 10.14445/22315381/IJETT-V67I9P208|
MLA Style: Sandhya, Nidhi B.Satija, Priyank Singhal "Green and Sustainable FPGA Based Counter For IOT Based Processor" International Journal of Engineering Trends and Technology 67.9 (2019):51-54.
APA Style:Sandhya, Nidhi B.Satija, Priyank Singhal. Green and Sustainable FPGA Based Counter For IOT Based Processor International Journal of Engineering Trends and Technology, 67(9), 51-54.
In the era of Industry 4.0, where billions of devices are connected together with the help of Artificial Intelligence, Internet of Things (IOT), Internet of Everything(IOE) and many more technologies which processes lots of data for getting the user equipped with information as these technologies are great advantage of the human beings but for the efficient use of energy for our digital devices that would be harmless for our environment and hence we opt for green computing. Therefore, in our work we have design green FPGA based counter which proves to be the heart of digital devices and hence tried to reduce the energy consumption of digital devices. So, design 64-bit FPGA based counter we have worked with Virtex-7 series family in combination with Verilog, HDL and Xilinx ISE Simulator. here, we have worked with 15 series IO Standards that are LVCMOS15, SSTL15, and LVDCI_15. we have calculated the total power consumption at constant voltage 0.970. In our work, we have found significant power reduction FPGA based 64-bit counter to 54.79%by applying LVCMOS15 IO Standard at volt 0.970.
 A Saxena,C Patel,M.Khan “Energy Efficient ALU Design Based On Voltage Scaling” in Gyancity Journal of Electronics and Computer Science,Vol.1, No.1, pp.29-33, September 2016ISSN: 2446–2918 DOI: 10.21058/gjecs.2016.11006.
 Michael Gschwind. Reprogrammable hardware for educational purposes. In Proc. of the 25th ACM SIGCSE Symposium, Phoenix, AZ, March 1994. ACM.
 A Saxena, A Bhatt, P Gautam, P Verma, C Patel,”High Performance FIFO Design for Processor through Voltage Scaling Technique” In Indian Journal of Science and Technology Vol 9(45), DOI: 10.17485/ijst/2016/v9i45/106916, December 2016
 Xu LY. Realization of UART Communication Based on FPGA. Microcomputer Information. 2007; 23(35):218–9.
 A Saxena, A Bhatt, P Gautam, P Verma, C Patel “Designing Power Efficient Fibonacci Generator Using Different FPGA Families ” International Journal of Engineering and Technology (IJET) DOI: 10.21817/ijet/2018/v10i2/181002065
 W.K. Huang and F. Lombardi, “An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays,14th
 IEEE VLSI Test Symposium, pp. 450-455, Princeton, NJ,USA, May
 1996. A Saxena, A Bhatt, C Patel “SSTL IO Based WLAN Channel Specific Energy Efficient RAM Design for Internet of Thing” 2018 3rd International Conference On Internet of Things: Smart Innovation and Usages (IoT-SIU) DOI: 10.1109/IoT-SIU.2018.8519899
 M. Renovell, J. Figueras, Y. Zorian, “Test of RAM-Based FPGA: Methodology and Application to the Interconnect”, 15th IEEE VLSITest
 A Saxena, S Gaidhani, A Pant, C Patel “Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA” in International Journal of Computer Trends and Technology (IJCTT) – Volume X Issue Y- Month
 A Saxena, S Sharma,P Agarwal, C Patel “SSTL Based Energy Efficient FIFO Designfor High Performance Processor ofPortable Devices ” in International Journal of Engineering and Technology (IJET)Vol 9 No 2
 A Saxena, A Bhatt, P Gautam, P Verma, C Patel,”High Performance FIFO Design for Processor through Voltage Scaling Technique” In Indian Journal of Science and Technology Vol 9(45), DOI: 10.17485/ijst/2016/v9i45/106916, December 2016.
 W.-J. Lee, G-E Kim, G-W Moon, and S-K Han, “A new phase-shifted full bridge converter with voltage-doubler-type rectifier for high-efficiency PDP sus-taining power modules,”IEEE Trans.Ind.Electron.,vol. 55, no. 6, pp. 2450– 2458, Jun. 2008.
 Lee, Jay & Davari, Hossein & Singh, Jaskaran & Pandhare,Vibhor. (2018). Industrial Artificial Intelligence for Industry 4.0-based Manufacturing Systems. Manufacturing Letters .18.10.1016/ j.mfglet.2018.09.002.
 R. Hill, J. Devitt, A. Anjum and M. Ali, "Towards In- TransitAnalytics for Industry 4.0," 2017IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data (SmartData), Exeter, 2017, pp. 810-817 doi:10
AI , FPGA, IOT, Industry 4.0,counter , HDL, Verilog, Xilinx ISE Simulator.