A New Dual-Differential Full-Adder Design for CED-based Fault-Tolerant Circuits

A New DualDifferential FullAdder Design for CEDbased FaultTolerant Circuits

© 2021 by IJETT Journal
Volume-69 Issue-12
Year of Publication : 2021
Authors : Mouna Karmani, Noura Ben Hadjyoussef, Belgacem Hamdi, Mohsen Machhout
DOI :  10.14445/22315381/IJETT-V69I12P231

How to Cite?

Mouna Karmani, Noura Ben Hadjyoussef, Belgacem Hamdi, Mohsen Machhout, "A New DualDifferential FullAdder Design for CEDbased FaultTolerant Circuits," International Journal of Engineering Trends and Technology, vol. 69, no. 12, pp. 257-266, 2021. Crossref, https://doi.org/10.14445/22315381/IJETT-V69I12P231

In this work, we present a new dual-differential full-adder bit-slice design that can be used for implementing circuits with Concurrent Error Detection (CED) capability. The proposed design is suitable to realize applications needing diagnostics and maintenance in the field. The proposed design used a mixed DPL/PTL logic style design, requires only 24 transistors, and provides dual-differential outputs. To prove the proposed design efficiency, the circuit is designed and simulated using the standard 32 nm technology node. The proposed scheme can be used to ameliorate the circuit fault detection, fault-masking, and then fault tolerance capability. By using the proposed full-adder bit-slice, we have implemented and simulated a 4-bit ripple carry adder design realized using a mixed CMOS/DPL/PTL logic style design. The simulation results prove the acceptable electrical behavior of the implemented 4-bit ripple carries adder design.

full-adder; dual-differential; CED; 32nm technology node;

[1] Karmani M, Benhadjyoussef N, Hamdi B, Machhout M, The DFA/ DFT?based hacking techniques and countermeasures: A case study of the 32?bit AES encryption crypto?core,. IET Comput. Digit. Tech, (2021) 160–170.
[2] J.Hua, Y. Peng, Y. Xu†, K. Cao, J. Jia, Makespan Minimization for Multiprocessor Real-Time Systems under Thermal and Timing Constraints, Journal of Circuits, Systems and Computers 28, (2019).
[3] K. Roy, S. Mukhopadhyay, and H. M.-Meimand, Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits, Proceedings of the IEEE, 91(2) (2003) 302-327.
[4] S. Yang, W. Wolf, N. Vijaykrishnan, Y. Xie and W. Wang, Accurate Stacking Effect Macro-modeling of Leakage Power in Sub-100nm Circuits, Proc. Int. Conference on VLSI Design, (2005) 165-170.
[5] Z. Cheng, M. Johnson, L. Wei, and K. Roy, Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks, Proc. Int. Symposium Low Power Electronics and Design, (1998) 239-244.
[6] R. X. Gu and M. I. Elmasry, Power Distribution Analysis and Optimization of Deep Submicron CMOS Digital Circuit, IEEE J. Solid-State Circuits, 31(5) (1996) 707-713.
[7] D. Zhu and H. Aydin, Reliability effects of process and thread redundancy on-chip multiprocessors, in Proc. 36th Annu. IEEE/IFIP Int. Conf. Dependable Syst. Networks, (2006) 212–213.
[8] Biswal, P.K., Biswas, S, A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits with Dynamic and Static C-elements, J Electron Test 35, (2019) 715–727.
[9] M. Karmani, C. Khedhiri, B. Hamdi, K.L. MAN, e.g., LIM, C. LEI, A Concurrent error detection and correction based fault-tolerant XOR-XNOR circuit for highly reliable applications, IAENG Transactions on Electrical Engineering , 1 (2013) 56-69.
[10] S. R. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas, VARIUS: A model of process variation and resulting timing errors for microarchitectures, in IEEE Transactions on Semiconductor Manufacturing, (2008).
[11] E. F. Hitt and D. Mulcar, Fault-Tolerant Avionic, CRC Press LL, (2001).
[12] D. Das and N. A. Touba, Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes, Journal of Electronic Testing: Theory and Applications, 15(1/2) 145-155 (1999).
[13] N. Joshi, K. Wu, J. Sundararajan, and R. Karri, Concurrent Error Detection for Evolutional Functions with applications in Fault-Tolerant Cryptographic Hardware Design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(6) (2006) 1163–1169.
[14] C. Zeng and E. J. McCluskey, Finite State Machine Synthesis with Concurrent Error Detection, Proc. International Test Conference, (1999) 672-679.
[15] C. Khedhiri, M. Karmani, B. Hamdi, and K. L. Man, Concurrent Error Detection Adder Based on Two Paths Output Computation, IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications Workshops, (2011) 27-32.
[16] M. Nicolaidis, On-line testing for VLSI: state of the art and trends, Integration, the VLSI Journal, 26(1-2) (1998) 197-209.
[17] P. Oikonomakos and M. Zwolinski, On the Design of Self-Checking Controllers with Datapath Interactions, in IEEE Transactions on Computers, 55(11) (2006) 1423-1434.
[18] Bin Talib, G.H., El-Maleh, A.H. & Sait, S.M., Design of Fault-Tolerant Adders: A Review, Arab J Sci Eng 43, (2018) 6667–6692.
[19] Marc Hunger and Sybille Hellebrand, Verification and Analysis of Self-Checking Properties through ATPG, 14th IEEE International On-Line Testing Symposium, Rhodes, Greece, (2008) 6 – 9.
[20] P. Oikonomakos and M. Zwolinski, On the Design of Self-Checking Controllers with Data path Interactions, in IEEE Transactions on Computers, 55(11) (2006) 1423 – 1434.
[21] E. Sicard, Microwind and Dsch version 3.1, INSA Toulouse, ISBN 2-87649-050-1, (2006).
[22] M. Nicolaidis., Efficient implementations of self-checking adders and alus, in 23rd International Symp, On Fault-Tolerant Computing, (1993) 586-595.
[23] D. Rajkumar, P. K. Dutta, S. K. Sarkar., Design and implementation of 4-bit ripple carry adder using SETMOS architecture, 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), (2016) 58-61.
[24] Akbar, M.A.; Wang, B.; Bermak, A. A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization. Electronics, 10 (2021) 1791.