Investigation of Duty Cycle Distortion in Clock Channels with Infinisim Clockedge Technology

Investigation of Duty Cycle Distortion in Clock Channels with Infinisim Clockedge Technology

© 2022 by IJETT Journal
Volume-70 Issue-4
Year of Publication : 2022
Authors : Sumitha Manoj, Dr. R. Surendiran
DOI :  10.14445/22315381/IJETT-V70I4P238

How to Cite?

Sumitha Manoj, Dr. R. Surendiran, "Investigation of Duty Cycle Distortion in Clock Channels with Infinisim Clockedge Technology," International Journal of Engineering Trends and Technology, vol. 70, no. 4, pp. 457-464, 2022. Crossref,

Infinisim has developed a dynamic clock analysis tool, clock edge Simulated Program with Integrated Circuit Emphasis (SPICE) provides accurate results at very high speed and full-chip capacity. The real-time adaptive simulation technology of RASER makes the simulation fast and accurate. Clock edge overcomes the limitations of Static Timing Analysis (STA) and provides the designer with accurate timing analysis, accurate power and leakage data, and On-Chip Variation (OCV) analysis. For accurate analysis of jitters in clock edges, Infinisim clock edge uses SPICE models instead of the .libs method. Earlier days, Prime Time (PT) was used with .libs to calculate the Jitter and delay. This investigation calculates the Duty Cycle Distortion (DCD) of clock sources using Infinisim clock edge. From the final observed results, it was found that the duty cycle is not to be varied as in the case of clock edge by synopsis prime time tool, and the results were found for only 50% duty cycle; hence the analysis also did not as accurate as clock edge.

Duty Cycle Distortion, Placement, and Routing (PnR), On Chip Variation, Node Based Framework (NBF), Static Timing Analysis, Prime Time, Infinisim Clock edge.

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