FPGA Implementation of 4-D DWT and BPS based Digital Image Watermarking

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2012 by IJETT Journal
Volume-3 Issue-2                          
Year of Publication : 2012
Authors :  S.Bhargav Kumar, K.Esther Rani


S.Bhargav Kumar, K.Esther Rani. " FPGA Implementation of 4-D DWT and BPS based Digital Image Watermarking". International Journal of Engineering Trends and Technology (IJETT). V3(2):234-238 Mar-Apr 2012. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group


In order to protect copyrighted material from illegal duplication, two typical technologies have been developed they are key - based cryptographic technique s and digital watermarks which enable the appropriate security during the trans mission process. A digital image watermark consists of signing an image with a signature or copyright message and the message is secretly embedded in the image by using a computer algorithm , using the signature the watermarked image will be detected and ex tracted. In our paper, w e propose a new technique of watermarking, combining both Discrete Wavelet Transform (DWT) and Bit - Plane Slicing ( BPS ) technique s. In the first unit , we decomposed the image to be watermarked in to four dimensional modified DWT coef ficients, by adding pseudo - random codes at the high and middle frequency bands of the DWT of an image. In the second unit , a key has been generated from LHLH frequency band s of the 4 - Level DWT image and this key is watermarked in to the original gray image . In the third unit , for data compression we used bit plane slicing technique where the original gray image is sliced in to 8 planes and we used bit plane 3 to embed in to the key watermarked image. The embedded key watermarked image is transmitted and the key watermarks are extracted with robustness. Using our technique , the processing time of the extraction of the watermark ha s been reduced and the peak signal - to - noise ratio ( PSNR ) value is improved . We implemented our technique using MATLAB and these uni ts are simulated, synthesized and optimized for Spartan - 3EDB FPGA chips using Active - HDL Version 7.2SE design tools.


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copyrighted material, cryptographic techniques, digital watermarks, signature, DWT , BPS , PSNR , Spartan - 3EDB FPGA, Active - HDL