Design and Analysis of CMOS and Adiabatic 4Bit Binary Multiplier

Design and Analysis of CMOS and Adiabatic 4-Bit Binary Multiplier

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2014 by IJETT Journal
Volume-7 Number-2                          
Year of Publication : 2014
Authors : Sonal Jain , Prof. Monika Kapoor
  10.14445/22315381/IJETT-V7P210

citation 

Sonal Jain , Prof. Monika Kapoor , Article: Design and Analysis of CMOS and Adiabatic 4-Bit Binary Multiplier, International Journal of Engineering Trends and Technology(IJETT), 7(2),71-74, published by seventh sense research group

Abstract

The power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high compatibility of VLSI systems used in various applications, the power dissipation in CMOS circuits arises from it’s switching activity ,which is influenced by the supply voltage and effective capacitance. The power dissipation can be reduced by adopting different design style. Adiabatic logic style is said to be an attractive solution for such low power electronic applications. The proposed technique has less power dissipation when compared to the conventional CMOS design style. This paper evaluates the 4-bit binary multiplier in different adiabatic logic style and their results were compared with conventional CMOS design. The simulation results indicates that the proposed technique is advantageous in many of low power digital applications.

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Keywords
Adiabatic logic, charge recovery, Low power, multiplier, Power supply