The Design of SET-CMOS Hybrid Logic Style of 1-Bit Comparator
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2015 by IJETT Journal | ||
| Volume-20 Number-5 |
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| Year of Publication : 2015 | ||
| Authors : A. T. Fathima Thuslim, Dr. V. Kannan |
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| DOI : 10.14445/22315381/IJETT-V20P244 |
Citation
A. T. Fathima Thuslim, Dr. V. Kannan"The Design of SET-CMOS Hybrid Logic Style of 1-Bit Comparator", International Journal of Engineering Trends and Technology (IJETT), V20(5),228-232 Feb 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
Single Electron Transistor is an Ultra-low power consumption as well as Ultra dense circuit formation is now possible with the help of mutual integration. These benefits have drawn the attraction of the future researchers to design the hybrid SET-CMOS style for future Nano-scale low power VLSI design. In this paper, we have designed at room temperature operable One bit Comparator circuit in hybrid SET-CMOS logic with considerably low power consumption. All the simulations are performed in SPICE MIB model for SET operation and BSIM4 for the operation of PMOS. The hybrid structure provides for better performance in respect to the conventional MOSFET structure.
References
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Keywords
SET, Hybrid CMOS-SET, 1 bit Comparator.