The Design of SET-CMOS Hybrid Logic Style of 1-Bit Comparator

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2015 by IJETT Journal
Volume-20 Number-5
Year of Publication : 2015
Authors : A. T. Fathima Thuslim, Dr. V. Kannan
DOI :  10.14445/22315381/IJETT-V20P244


A. T. Fathima Thuslim, Dr. V. Kannan"The Design of SET-CMOS Hybrid Logic Style of 1-Bit Comparator", International Journal of Engineering Trends and Technology (IJETT), V20(5),228-232 Feb 2015. ISSN:2231-5381. published by seventh sense research group


Single Electron Transistor is an Ultra-low power consumption as well as Ultra dense circuit formation is now possible with the help of mutual integration. These benefits have drawn the attraction of the future researchers to design the hybrid SET-CMOS style for future Nano-scale low power VLSI design. In this paper, we have designed at room temperature operable One bit Comparator circuit in hybrid SET-CMOS logic with considerably low power consumption. All the simulations are performed in SPICE MIB model for SET operation and BSIM4 for the operation of PMOS. The hybrid structure provides for better performance in respect to the conventional MOSFET structure.


1. Lageweg. al. Single electron encoded latches and flip flops, IEEE Trans. Nanotechnology 3(2, 237-248 (2004)
2. Wu, G., Cai, L., Kang: A 8 bit parity code generator based on multigate SET, IEEE, NEMS, 183-186 (2008)
3. Chen, Y.C.: Verification of reconfigurable binary decision diagram SE arrays, IEEE TCAD 32, 1473-1483 (2013)
4. Mizugaki Y. Blocking Charge Oscialltion in a series array of two tiny tunnel junctions with resistive ground path from its island. (2012), 194-192 IEEE Trans.
5. Shin, S.J., Jung, Park, Yoon, Silicon based ultra small multi switching SET operating at room temperature Appl. Physics., 97(10), (2010)
6. Karre, P.s. et al. Room temperature SET fabricated by focused ion beam deposition, Applied Physics 102(2), (2007), 0243161-0243164
7. Uchida, et. Al. Programmable SET logic for future low power intelligent LSI: proposal and room temperature operation, IEEE, Electron Devices 50(7), 1623-1630,(2003)
8. Inokawa, Takahash, A multiple valued logic and memory with combined Single electron and metal oxide semiconductor transistors, IEEE trans. Electron devices50(2), 462-470(2003)
9. Ionecu, S. Pott, Mahapatra, Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive, IEEE Electron devices Lett. 25(6), 411-413 (2004)
10. Gorter C.J., A possible explanation of the increase of the electrical resistance of thin metal flims at low temperatures and small field strengths. Physics 17(8), 777-780(1951)
11. Zhang, T. Kasai, Novel hybrid voltage controlled ring oscillators using SET and MOS transistor, IEEE, Nanotechnology 6(2), 170-175, 2007
12. Shin, Yang, S. R. Takahashi, Room temperature charge stability modulated by quantum effects in a Nano scale silicon island, Nano letter 11(4), 1591-197(2011)

SET, Hybrid CMOS-SET, 1 bit Comparator.