IJBTT

Design of Low Power L1 Cache Using CBF Based TOB Architecture in Embedded Processors

	International Journal of Engineering Trends and Technology (IJETT)
	© 2015 by IJETT Journal
	Volume-20 Number-6
	Year of Publication : 2015
	Authors : Mrs.S.Brindha, Ms.B.Kavitha
	DOI :  10.14445/22315381/IJETT-V20P252

Citation 

Mrs.S.Brindha, Ms.B.Kavitha "Design of Low Power L1 Cache Using CBF Based TOB Architecture in Embedded Processors", International Journal of Engineering Trends and Technology (IJETT), V20(6),263-269 Feb 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

In the embedded processor, a cache could consume 40% of the entire chip power. So, reduce the high power utilization of cache is very important. To reduce the high power utilization a new cache method is used in the embedded processors. This is termed as an Early Tag Access (ETA) method. For the memory instructions, the early target way can be found by this ETA. Thereby it can reduce the high power utilization. If the ETA does not find the way, it search the way in L1 Cache. So automatically the power gets increased. Here a new energy efficient matching mechanism referred to as Counting Bloom Filter (CBF) based Tag Overflow Buffer (TOB) is proposed. This TOB uses reduced number of tag bits thereby the power gets reduced. The ETA can be activating only when the TOB hit is occurred. Compared to the previous technique the power consumption gets decreased up to 40%.

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Key words
Cache, LSQ tag, LSQ TLB, LFSR, Comparator, Hass table, Low Power