Design of Low Power L1 Cache Using CBF Based TOB Architecture in Embedded Processors

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2015 by IJETT Journal
Volume-20 Number-6
Year of Publication : 2015
Authors : Mrs.S.Brindha, Ms.B.Kavitha


Mrs.S.Brindha, Ms.B.Kavitha "Design of Low Power L1 Cache Using CBF Based TOB Architecture in Embedded Processors", International Journal of Engineering Trends and Technology (IJETT), V20(6),263-269 Feb 2015. ISSN:2231-5381. published by seventh sense research group


In the embedded processor, a cache could consume 40% of the entire chip power. So, reduce the high power utilization of cache is very important. To reduce the high power utilization a new cache method is used in the embedded processors. This is termed as an Early Tag Access (ETA) method. For the memory instructions, the early target way can be found by this ETA. Thereby it can reduce the high power utilization. If the ETA does not find the way, it search the way in L1 Cache. So automatically the power gets increased. Here a new energy efficient matching mechanism referred to as Counting Bloom Filter (CBF) based Tag Overflow Buffer (TOB) is proposed. This TOB uses reduced number of tag bits thereby the power gets reduced. The ETA can be activating only when the TOB hit is occurred. Compared to the previous technique the power consumption gets decreased up to 40%.


[1] Jianwei Dai, Menglong Guan, and Lei Wang, “ Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors,” in IEEE transaction on very large scale integration (VLSI) systems, Vol. 22, No. 2, Feb 2014, pp. 396-407.
[2] Intel XScale Microarchitecture, Intel, Santa Clara, CA, USA, 2001.
[3] C. Zhang, F. Vahid, and W. Najjar “A highly-configurable cache architecture for embedded systems,” in Proc. 30th Annu. Int. Symp. Comput. Archit., Jun. 2003, pp. 136–146.
[4] S. Segars, “Low power design techniques for microprocessors,” in Proc. Int. Solid-State Circuits Conf. Tuts., Feb. 2001.
[5] S. Manne, A. Klauser, and D. Grunwald, “Pipline gating: Spculation conrol for energy reduction,” in Proc. Int. Symp. Comput. Archit., Jun.–Jul. 1998, pp. 132–141.
[6] M. Gowan, L. Biro, and D. Jackson, “Power considerations in the design of the alpha 21264 microprocessor,” in Proc. Design Autom. Conf., Jun. 1998, pp. 726–731.
[7] A. Malik, B. Moyer, and D. Cermak, “A Low power unified cache architecture providing power and performance flexibility,” in Proc. Int. Symp. Low Power Electron. Design, 2000, pp. 241–243.
[8] T. Lyon, E. Delano, C. McNairy, and D. Mulla, “Data Cache Design Considerations for the Itanium Processor,” in Proc. IEEE Int. Conf. Comput. Design, VLSI Comput. Process., 2002, pp. 356–362.
[9] D. Nicolaescu, A. Veidenbaum, and A. Nicolau, “Reducing power consumption for high-associativity data caches in embedded processors,” in Proc. Design, Autom., Test Eur. Conf. Exhibit., Dec. 2003, pp. 1064–1068.
[10] C. Zhang, F. Vahid, Y. Jun, and W. Najjar, “A way-halting cache for low-energy high-performance systems,” in Proc. Int. Symp. Low Power Electron. Design, Aug. 2004, pp. 126–131.
[11] J. Montanaro, R. T. Witek, K. Anne, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue, J. Eno, W. Hoeppner, D. Kruckemyer, T. H. Lee, P. C. M. Lin, L. Madden, D. Murray, M. H. Pearce, S. Santhanam, K. J. Snyder, R. Stehpany, and S. C. Thierauf, “A 160-MHz 32-b 0.5- W CMOS RISC microprocessor,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1703–1714, Nov. 1996.
[12] S. Santhanam, A. J. Baum, D. Bertucci, M. Braganza, K. Broch, T. Broch, J. Burnette, E. Chang, C. Kwong-Tak, D. Dobberpuhl, P. Donahue, J. Grodstein, K. Insung, D. Murray, M. Pearce, A. Silveria, D. Souydalay, A. Spink, R. Stepanian, A. Varadharajan, V. R. van Kaenel, and R. Wen, “A low-cost, 300-MHz, RISC CPU with attached media processor,” IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1829–1838, Nov. 1998.
[13] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A framework for architectural-level power analysis and optimizations,” in Proc. Int. Symp. Comput. Archit., Jun. 2000, pp. 83–94. [14] A. Moshovos, “RegionScout: Exploiting coarse-grain sharing in snoop-coherence,” in Proc. Ann. Int. Symp. Comput. Arch., Jun. 2005, pp. 234–245.
[15] A. Moshovos, G. Memik, B. Falsafi, and A. Choudhary, “Jetty: Filtering snoops for reduced energy consumption in smp servers,” in Proc. Ann. Int. Conf. High-Performance Comput. Arch., Feb. 2001, pp. 85–96.
[16] J. K. Peir, S. C. Lai, S. L. Lu, J. Stark, and K. Lai, “Bloom filtering cache misses for accurate data speculation and prefetching,” in Proc. Ann. Int. Conf. Supercomput., Jun. 2002, pp. 189–198. [17] S. Sethumadhavan, R. Desikan, D. Burger, C. R. Moore, and S. W. Keckler, “Scalable hardware memory disambiguation for high-ILP processors,” IEEE Micro, vol. 24, no. 6, pp. 118–127, Nov. 2004.
[18] B. Fagin, “Partial resolution in branch target buffers,” IEEE Trans. Comput., vol. 46, no. 10, pp. 1142–1145, Oct. 1997.
[19] B.-S. Choi and D.-I. Lee, “Cost-effective value prediction micro-operation using partial tag and narrow-width operands,” in Proc. IEEEPacific Rim Conf. Commun., Comput. Signal Process., Aug. 2001, pp. 319–322.
[20] L. Liu, “Partial address directory for cache access,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no. 2, pp. 226–240, Jun. 1994.
[21] R. Min, Z. Xu, Y. Hu, and W.-B. Jone, “Partial tag comparison: A new technology for power-efficient set-associative cache designs,” in Proc. 17th Int. Conf. VLSI Des. (VLSID), Jan. 2004, pp. 183–188.
[22] P. Petrov and A. Orailoglu, “Data cache energy minimizations through programmable tag size matching to the applications,” in Proc. Int. Symp. Syst. Synth. (ISSS), Sep./Oct. 2001, pp. 113–117.
[23] M. Peng, Y. Pan, and B. Liu, “Low energy partial tag comparison cache using valid-bit pre-decision,” in Proc. IEEE Region 10 Conf. (TENCON), Nov. 2006, pp. 1–4.
[24] H.-C. Chen and J.-S. Chiang, “Low-power way-predicting cache using valid-bit pre-decision for parallel architecture,” in Proc. 19th Int. Conf. Adv. Inf. Netw. Appl., Mar. 2005, pp. 203–206.

Key words
Cache, LSQ tag, LSQ TLB, LFSR, Comparator, Hass table, Low Power