IJBTT

Design and Analysis of a Floating Point Fused Multiply Add Unit using VHDL

	International Journal of Engineering Trends and Technology (IJETT)
	© 2015 by IJETT Journal
	Volume-24 Number-4
	Year of Publication : 2015
	Authors : Farouq Aliyu
	DOI :  10.14445/22315381/IJETT-V24P232

Citation 

Farouq Aliyu"Design and Analysis of a Floating Point Fused Multiply Add Unit using VHDL", International Journal of Engineering Trends and Technology (IJETT), V24(4),169-176 June 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Ever since the growth of processing speed began to slow down due to immense heat generated by the processing units, engineers started looking for other speed up alternatives. One of such is the ”Fuse Multiply Add” (FMA) unit. This unit combines multiplication of two operands and their summation with third operand as a single instruction. As a result, a floating point primitive is created out of the two arithmetic operations. This paper describes the design and development of a FMA. It also points out the limitations of the FMA using VHDL programming language. Furthermore, the paper points the mechanics of the different parts of the FMA in order to shade more light on those parts of the FMA that prove costly in terms of speed, power and area.

 References

[1] K.-Y. Wu, C.-Y. Liang, K.-K. Yu, and S.-R. Kuang, “Multiple-mode floating-point multiply-add fused unit for trading accuracy with power consumption,” in Computer and Information Science (ICIS), 2013 IEEE/ACIS 12th International Conference on. IEEE, 2013, pp. 429– 435.
[2] N. T. Quach and M. J. Flynn, Suggestions for implementing a fast IEEE multiply-add-fused instruction. Computer Systems Laboratory, Stanford University, 1991.
[3] E. Quinnell, E. Swartzlander, and C. Lemonds, “Floating-point fused multiply-add architectures,” in Signals, Systems and Computers, 2007. ACSSC 2007. Conference Record of the Forty-First Asilomar Conference on, Nov 2007, pp. 331–337.
[4] R. Montoye, E. Hokenek, and S. Runyon, “Design of the ibm risc system/6000 floating-point execution unit,” IBM Journal of Research and Development, vol. 34, no. 1, pp. 59–70, Jan 1990.
[5] C. N. Hinds and D. R. Lutz, “A small and fast leading one predictor corrector circuit,” in Proc. 39 Asilomar Conference on Signals, Systems and Computers, 2005, pp. 1181–1185.
[6] E. Hokenek, R. Montoye, and P. Cook, “Second-generation risc floating point with multiply-add fused,” Solid-State Circuits, IEEE Journal of, vol. 25, no. 5, pp. 1207–1213, Oct 1990.
[7] N. T. Quach and M. J. Flynn, Leading one prediction–Implementation, generalization, and application. Computer Systems Laboratory, Stanford University, 1991.
[8] I. Koren, Computer arithmetic algorithms. Universities Press, 2002.
[9] L. Louca, T. Cook, and W. Johnson, “Implementation of ieee single precision floating point addition and multiplication on fpgas,” in FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on, Apr 1996, pp. 107–116.
[10] P. Seidel, “Multiple path ieee floating-point fused multiply-add,” in Proceedings of The IEEE Midwest Symposium On Circuits And Systems, vol. 46, no. 3. LIDA RAY TECHNOLOGIES INC.,, 2003, p. 1359.
[11] J. He and Y. Zhu, “Design and implementation of a quadruple floatingpoint fused multiply-add unit,” in Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering. Atlantis Press, 2013.
[12] P. Ashenden, The Designer’s Guide to VHDL, ser. Systems on Silicon. Elsevier Science, 2010. [Online]. Available: https: //books.google.com.sa/books?id=XbZr8DurZYEC
[13] F. M. Aliyu, “Fma source code,” 2015. [Online]. Available: https://www.researchgate.net/profile/Farouq Aliyu/contributions
[14] Xilinx, “7 series fpgas overview,” 2015. [Online]. Available: http://www.xilinx.com/support/documentation/data sheets/ds180 7Series Overview.pdf

Keywords
Computer Arithmetic, Fused Multiply-Add, FMA, IEEE Floating-point, Leading Zero Detector, Leading Zero Anticipator.