A Survey on Leakage Reduction on Logic Gate in Deep Submicron Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2016 by IJETT Journal
Volume-35 Number-5
Year of Publication : 2016
Authors : Md Tauseef, Sudeep Sharma, Rita Jain
DOI :  10.14445/22315381/IJETT-V35P249

Citation 

Md Tauseef, Sudeep Sharma, Rita Jain"A Survey on Leakage Reduction on Logic Gate in Deep Submicron Technology", International Journal of Engineering Trends and Technology (IJETT), V35(5),228-232 May 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
The popularity and necessity of portable electronic systems by users have strongly influenced VLSI designers to make great effort for reduced silicon area, improved speeds, long duration battery life, and great reliability. The VLSI designers always try to save power consumption while designing a system. The performance of circuit is strongly influenced by the choice of logic style to design the digital circuit. Design optimization at circuit level is very important to avoid any degradation in output voltage level, to achieve less power consumption, to have less propagation delay in critical path and to be reliable at reduced supply voltage as we scale down towards deep sub micron technology. Switching activity of circuit affects the dynamic power consumption but with the technology scaling, the number of transistors is continuously reduced which increases the static leakage power at lower supply voltage. In a few technology generations, leakage power is supposed to become a main contributor of total power consumption. In this Paper we calculate impact of leakage power on conventional gate at 45nm and 32nm technology by using HSPICE simulator at supply voltage of 0.9V and 1V with 250C and 1000C at 10MHz frequency.

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Keywords
Leakage Power, Subthreshold Current, Gate oxide Current, Shorter channel Effect.