The Design of High Speed FIR Filter using Improved DA Algorithm and it’s FPGA Implementation

The Design of High Speed FIR Filter using Improved DA Algorithm and it’s FPGA Implementation

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2012 by IJETT Journal
Volume-3 Issue-2                          
Year of Publication : 2012
Authors :  Magatha Nayak Bhukya, K. Anjaiah, G. Sravya, P. Nagaraju

Citation 

Magatha Nayak Bhukya, K. Anjaiah, G. Sravya, P. Nagaraju. "The Design of High Speed FIR Filter using Improved DA Algorithm and it’s FPGA Implementation". International Journal of Engineering Trends and Technology (IJETT). V3(2):123-126 Mar-Apr 2012. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

when the DA (distributed arithmetic) algorithm is directly applied in FPGA (field programmable gate array) to realize FIR (finite impulse response) filter, it is difficult to achieve the best configuration in the coefficient of FIR filter, the storage resource and the computing speed. According to this problem, the paper provides the detailed analysis a nd discussion in the algorithm, the memory size and the look - up table speed. Also, the corresponding optimization and improvement measures are discussed and the concrete Hardware realization of the circuit is presented. The design based on Altera EP2C5T144 C8 chips is synthesized under the integrated environment of QUARTUS II 7.1. The results of Simulation and test show that this method greatly reduces the FPGA hardware resource and the high speed filtering is achieved. The design has a big breakthrough comp ared to the traditional FPGA realization.

References

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Keywords
FIR filter, DA algorithm, FPGA.