A Darlington Pair Based CMOS Two Stage Operational Amplifier at 32nm Technology

A Darlington Pair Based CMOS Two Stage Operational Amplifier at 32nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-43 Number-1
Year of Publication : 2017
Authors : Vinamrata Yadav, Nikhil Saxena, Amit Rajput
DOI :  10.14445/22315381/IJETT-V43P209

Citation 

Vinamrata Yadav, Nikhil Saxena, Amit Rajput "A Darlington Pair Based CMOS Two Stage Operational Amplifier at 32nm Technology", International Journal of Engineering Trends and Technology (IJETT), V43(1),53-57 January 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
The low power chip designing is a field of immense interest to the technology for electronics chip designing industries. Operational amplifiers (Op-Amps) are an integral parts of many analog and mixed signal systems. There is need to investigate the performance of the forthcoming scaled channel length CMOS devices. In this work a two stage CMOS Operational Amplifier with gain boosting technique, Darlington pair is proposed. The proposed Op-Amp shows high gain as well as high CMRR with reduced leakage current and power supply. This amplifier is highly useful for wireless communication because of low power consumption, high bandwidth, high gain and high CMRR. The designed operational amplifier gain is 93 dB, Unity-Gain Bandwidth is 538 MHz, CMRR is 100dB, slew rate is 20.13V/µS, power dissipation is 10pW, leakage current is 2.17pA, phase margin is 86º, and settling time is 95ns. The designed circuit is simulated using H-Spice tool at 32nm technology.

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Keywords
—Two Stage CMOS Operational Amplifier, Spice Tool, Darlington Pair, Gain, CMRR, Leakage Current, and Power Dissipation.