Implementation of Aging-Aware Multiplier Design for Area and Power Critical Applications
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2017 by IJETT Journal | ||
| Volume-44 Number-2 |
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| Year of Publication : 2017 | ||
| Authors : A.Prasanna Lakshmi, S. Prabhu Das |
Citation
A.Prasanna Lakshmi, S. Prabhu Das "Implementation of Aging-Aware Multiplier Design for Area and Power Critical Applications", International Journal of Engineering Trends and Technology (IJETT), V44(2),85-90 February 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
The main constraint in VLSI system design is to achieve low power devices. In any digital filter, multipliers are the major elements. The throughput is the major parameter of multiplier that influences the performance of multiplier. For long term usage, aging becomes the main constraint that affects the performance of the system. Majorly aged systems fail due to delay problems. There are many approaches to design multipliers that reduce this aging effect. But these systems require large area, power. Moreover, timing violations occur when fixed latency designs are used. For reducing these timing violations and for implementing an aging reliable low power multiplier, adaptive hold logic is used. The transistor speeds are influenced by both negative and positive bias temperatures, for long term applications due to aging effect, the system may fail to perform because of timing violations. Therefore, it is necessary to implement the high performance designs. Here we propose a reversible Wallace Tree multiplier design with razor flip flop based multiplier circuit. This design is able to provide high throughput for area power critical applications. The proposed method can be digital filters to enhance the performance in the real time environment.
References
[1] Y. Cao. (2013). Predictive Technology Model (PTM) and NBTI Model [Online]. Available: http://www.eas.asu.edu/?ptm
[2] S. Zafaret al., “A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates,” in Proc.IEEESymp. VLSI Technol. Dig. Tech. Papers, 2006, pp. 23–25.
[3] S. Zafar, A. Kumar, E. Gusev, and E. Cartier, “Threshold voltage instabilities in high-k gate dielectric stacks,” IEEE Trans. Device Mater.Rel., vol. 5, no. 1, pp. 45–64, Mar. 2005.
[4] H.-I. Yang, S.-C.Yang, W. Hwang, and C.-T. Chuang, “Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM,” IEEE Trans. Circuit Syst., vol. 58, no. 6, pp. 1239–1251, Jun. 2011.
[5] R. Vattikonda, W. Wang, and Y. Cao, “Modeling and miimization of pMOS NBTI effect for robust naometer design,” in Proc. ACM/IEEEDAC, Jun. 2004, pp. 1047–1052.
[6] H. Abrishami, S. Hatami, B. Amelifard, and M. Pedram, “NBTI-aware flip-flop characterization and design,” in Proc. 44th ACM GLSVLSI, 2008, pp. 29–34.
[7] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “NBTI-aware synthesis of digital circuits,” in Proc. ACM/IEEE DAC, Jun. 2007, pp. 370–375.
[8] A. Calimera, E. Macii, and M. Poncino, “Design techniqures for NBTItolerant power-gating architecture,” IEEE Trans. Circuits Syst., Exp.Briefs, vol. 59, no. 4, pp. 249–253, Apr. 2012.
[9] K.-C. Wu and D. Marculescu, “Joint logic restructuring and pin reordering against NBTI-induced performance degradation,” in Proc. DATE, 2009, pp. 75–80.
[10] Y. Lee and T. Kim, “A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs,” in Proc. ASPDAC, 2011, pp. 603–608.
Keywords
The proposed method can be digital filters to enhance the performance in the real time environment.