Simulation study of CMOS based 6 Transistors SRAM

Simulation study of CMOS based 6 Transistors SRAM

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-44 Number-5
Year of Publication : 2017
Authors : Dr. M. Nizamuudin
DOI :  10.14445/22315381/IJETT-V44P243

Citation 

Dr. M. Nizamuudin "Simulation study of CMOS based 6 Transistors SRAM", International Journal of Engineering Trends and Technology (IJETT), V44(5),218-220 February 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
In this paper we computes the Static Noise Margin , Power consumption of 6T SRAM at different voltage supply and temperature. Further, the Simulation of various Waveforms of the 6T SRAM have been presented. SNM is present in SRAM cell which is effect the stability in read operation of the 6T SRAM cells. SRAM cell stability analysis is a based on Static Noise Margin (SNM) investigation when in read mode, although many memory errors may occur during read operations. In this paper we investigate the SRAM cell SNM during read operations analyzing various alternatives to improve cell stability in this mode. We show that it is possible to improve cell stability during read operations while reducing word line voltage by SNM.

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Keywords
Power Consumption, Cell Ratio, CMOS, Pull-up Ratio, Static Noise Margin (SNM), VLSI.