Compression and Decompression of Embedded System Codes

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-45 Number-7
Year of Publication : 2017
Authors : E.Silvia Helan, Mr. P.M.Sandeep, Mr.V.Suresh Babu, Mr. M. Varatharaj
DOI :  10.14445/22315381/IJETT-V45P268

Citation 

E.Silvia Helan, Mr. P.M.Sandeep, Mr.V.Suresh Babu, Mr. M. Varatharaj "The Production of Green sustainable Fuel From Castor Oil", International Journal of Engineering Trends and Technology (IJETT), V45(7),325-330 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Embedded system depends on three factors such as performance, power consumption and cost. Memory is a key factor in such systems. Code compression is a technique used in embedded system to reduce the memory usage .It has two methods such as Bit Mask code compression and dictionary based code compression. The Bit Mask code compression is to record mismatched values and their positions to reduce the greater number of instruction. In order to reduce the code word length of high frequency instruction Bit Mask algorithm is used. In addition, a novel dictionary selection algorithm was proposed to increase the instruction match rates. Compression ratio is placed in embedded system as a key factor for memory. The compression ratio is a metric used to evaluate memory compression efficiency (compressed code size divided by original code size).So, as a result it can achieve 7.5% improvement in the compression ratio. Furthermore, the code compression technique is used by Bit Mask compression, dictionary based code compression and Golomb coding.

 References

[1] Wei Jhih Wang and Chang Hong Lin, “Code Compression for Embedded Systems Using Separated Dictionaries,’’ IEEE Transaction on very large scale integration (VLSI) Systems, Vol. 24, NO. 1, Jan. 2016.
[2] A. Wolfe and A. Chanin, “Executing compressed programs on an embedded RISC architecture,” in Proc. 25th Annu. Int. Symp.Microarchitecture, Dec. 1992, pp. 81–91.
[3] C. Lefurgy, P. Bird, I.-C. Chen, and T. Mudge, “Improving code density using compression techniques,” in Proc. 30th Annu. ACM/IEEE Int.Symp. MICRO, Dec. 1997, pp. 194–203.
[4] S.-W. Seong and P. Mishra, “A bitmask-based code compression technique for embedded systems,” in Proc. IEEE/ACM ICCAD, Nov. 2006, pp. 251–254.
[5] S.-W. Seong and P. Mishra, “An efficient code compression technique using application-aware bitmask and dictionary selection methods,” in Proc. DATE, 2007, pp. 1–6.
[6] H. Lekatsas and W. Wolf, “SAMC: A code compression algorithm for embedded processors,” IEEE Trans. Computer-Aided Design Integr.Circuits Syst., vol. 18, no. 12, pp. 1689–1701, Dec. 1999.
[7] S. Y. Larin and T. M. Conte, “Compiler-driven cached code compression schemes for embedded ILP processors,” in Proc. 32nd Annu. Int. Symp.Microarchitecture, Nov. 1999, pp. 82–91.
[8] Y. Xie, W. Wolf, and H. Lekatsas, “Code compression for VLIW processors using variable-to-fixed coding,” in Proc. 15th ISSS, 2002, pp. 138–143.
[9] C. H. Lin, Y. Xie, and W. Wolf, “Code compression for VLIW embedded systems using a self-generating table,” IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 15, no. 10, pp. 1160–1171, Oct. 2007.
[10] C.-W. Lin, C. H. Lin, and W. J. Wang, “A Power-aware code compression design for RISC/VLIW architecture,” J. Zhejiang Univ.-Sci.C (Comput. Electron.), vol. 12, no. 8, pp. 629–637,Aug.2011.

Keywords
Computer architecture, dictionary-based codecompression (DCC), embedded systems, separated dictionaries