Implementation of Adaptive Viterbi Decoder

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2013 by IJETT Journal
Volume-4 Issue-2                       
Year of Publication : 2013
Authors : Devendra Made , R.B. Khule , Dipak Iwanate

Citation 

Devendra Made , R.B. Khule , Dipak Iwanate. "Implementation of Adaptive Viterbi Decoder". International Journal of Engineering Trends and Technology (IJETT). V4(2):153-159 Feb 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

Viterbi algorithm is employed in wireless communication to decode the convolutional codes; those codes are used in every robust digital communication systems. Such decoders are complex & dissipiate large amount of power. Thus the paper presents the design of an Adaptive Viterbi Decoder (AVD) that uses survivor path with parameters for wireless communication in an attempt to reduce the power and cost and at the same time increase in speed. Most of the researches work to reduce power consumption, or work with high frequency for using the decoder in the modern applications such as 3 GPP, DVB, and wireless communications. Field Programmable Gate Array technology (FPGA) is considered a highly configurable option for implementing many sophisticated signal Processsing tasks. The proposed decoder design is implemented on Xilinx Spartan 3 , XC3S200 FPGA chip using VHDL code and Xilinx ISE 9.1 used for synthesis.

References

[1] Prof. Siddeeq Y. Ameen,Mohammed H. Al - Jammas and Ahmed S. Alenezi,” FPGA Implementation of Modified Architecture for Adaptive Viterbi Decoder”IEEE,2011.
[2] S. W. Shaker, S. H. Alramely and K. A. Shehata, “Design and implementation of low - power Viterbi decoder for software - defined WiMAX receiver”, 17th Telecommunication Forum TELFOR, Serbia, Belgrade, 2009
[3] H. .S, Suresh and B. .V, Ramesh, “FPGA imp lementation of Viterbi decoder”, Proceedings of the 6th WSEAS Int. Conf. on Electronics, Hardware, Wireless and Optical Communications, Corfu Island, Greece, February 16 - 19, 2007.
[4] J. S, Reeve., and K. Amarasinghe "A parallel Viterbi decoder for block c yclic and convolutional codes", Journal of Signal Processing, vol. 86, page 278, 2006.
[5] Obeid A. M., Ortiz A. G., Ludewig R., and Glenser M., "Prototype of a high performance generic Viterbi decoder", Proceedings. 13th IEEE International Workshop on Rap id System Prototyping I 2002.
[6] J. Bhasker “VHDL Prime r” PHI publication third editio

Keywords
FPGA, VHDL, AVD, AWGN,DoD, VHSIC.