Simulation of Integer N Frequency Synthesizer
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International Journal of Engineering Trends and Technology (IJETT) | 
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| © 2013 by IJETT Journal | ||
| Volume-4 Issue-6 |
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| Year of Publication : 2013 | ||
| Authors : Vemula Lohith Kumar |
Citation
Vemula Lohith Kumar."Simulation of Integer N Frequency Synthesizer". International Journal of Engineering Trends and Technology (IJETT). V4(6):2662-2665 Jun 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group.
Abstract
This document implements oscillator in the up conversion and down conversion of wireless transceivers using Integer N Frequency synthesizer with an external loop filter and VCO. The Easiest way to design and simulate Frequency synthesizer and lock the PLL. It can implement practically at high frequ encies.
References
[1]. Mike Curtin and Paul O`Brien, "Phase - Locked Loops for High - Frequency Receivers and Transmitters"
[2]. Dean Banerjee, PLL Performance, Simulation and Design, 3rd Edition, Dean Banerjee Publications, 2003, ISBN: 0970820712
[3]. Brendan Daly, "Comparing Integer - N and Fractional - N Synthesizers," Microwaves and RF, September 2001, pp. 210 - 215.
[4]. Jae Hwan Lee, Hang Geun Jeong, "Computer Simulation Results for a W - CDMA Frequency Synthesizer," isitc, pp.383 - 386, 2007 International Symposium on Information Technology Convergence (ISITC 2007), 2007
[5]. “ An ultra - low power integer - N frequency synthesizer for MICS transceivers ” authored by Su Cui a , Venkatesh Acharya b , Bhaskar Banerjee c in Microelectronics journal
[6]. ”A Stabilization Technique for Phase - Locked Frequency Synthesizers” authored by Tai - Cheng Lee and Be hzad Razavi, in IEEE journal of solid state circuits.
[7]. Design Tool: ADISIMPLL, Analog Devices, Inc.
[8]. Analog Devices PLL Product Portfolio: http://www.analog.com/pll
[9]. Ana log Devices Datasheet of ADF4106.
Keywords
ADF4106, ADSIMPLL, Pulse Swallow Function.