Design of Vedic Multiplier for Digital Signal Processing Applications

Design of Vedic Multiplier for Digital Signal Processing Applications

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2013 by IJETT Journal
Volume-4 Issue-7                      
Year of Publication : 2013
Authors : R.Naresh Naik , P.Siva Nagendra Reddy , K. Madan Mohan

Citation 

R.Naresh Naik , P.Siva Nagendra Reddy , K. Madan Mohan. "Design of Vedic Multiplier for Digital Signal Processing Applications". International Journal of Engineering Trends and Technology (IJETT). V4(7):3025-3030 Jul 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group.

Abstract

Multiplier is one of the most important part in any processor speed which improves the speed of the operation like in special application processors li ke Digital Signal Processor (DSPs).To Increase the speed of operation we should take care of the precision previously we used the floating point multipliers which were consume more silicon area and take more clock frequency than fixed point (Q - format) mult ipliers. Now we propose a method which is faster multiplication technique by using Vedic mathematics formula Urdhava Tiryakbhyam method which means vertically and cross wire. All the operations in Vedic multiplier were executed concurrently and also we wil l get the output same as input bit length so Vedic multiplier is time, space and power efficient .The coding is done for 16 - bit (Q - 15) and 32 - bit (Q - 31) fractional fixed point multiplications using Verilog and synthesized using Xilinx ISE version 14.3. Fur ther the speed comparisons of this multiplier with Normal Booth multiplier were presented. The results clearly show that our Urdhava Tiryakbhyam multiplier can have great amount of impact on the DSP applications to improve the execution speed of the DSP pr ocessors when compared to other multipliers.

References

[1] Jagadguru Swami Sri Bharati Krishna Tirthaji Maharaja, “ Vedic Mathematics: Sixteen Simple Math ematical Formulae from the Veda ,” Motilal Banarasidas Publishers, Delhi, 2009, pp. 5 - 45.
[2] Sandesh S. Saokar. R. M. Banakar. Saroja Siddamal. , “ High Speed Signed Multiplier for Digital Signal . Processing Applications , ”ieee 2012.
[3] Himanshu Thapliyal a nd M. B. Srinivas,“An efficient method of elliptic curve encryption using Ancient Indian Vedic Mathematics , ”48th IEEE International Midwest Symposium on Circuits and Systems, 2005, vol. 1, pp. 826 - 828.
[4] M. Pradhan and R. Panda, “ Design and Implementat ion of Vedic Multiplier, ” A.M.S.E Journal, Computer Science and Statistics, France vol. 15, July 2010, pp. 1 - 19.
[5] Harpreet Singh Dhillon , Abhijit Mitra, “ A Reduced - Bit Multiplication Algorithm for Digital Arithmetics, ” International Journal of Comput ational and Mathematical Sciences, Spring 2008, pp.64 - 69.
[6] Sen - Maw Kuo and Woon - Seng Gan, “ Digital Signal Processor, architectures ,implementations and applications, ” Pearson Prentice Hall, 2005, pp. 253 - 323.
[7] S. S. Kerur, Prakash Narchi, Jayashree C .N., Harish M.Kittur and GirishV.A.“ Implementation of Vedic Multiplier for Digital Signal Processing ,” International Journal of Computer Applications, 2011, vol. 16, pp. 1 - 5.

Keywords
Q - format, Urdhava Tiryakbhyam, Vedic Mathematics, Fractional fixed point.