Comparative Analysis of Low power, high speed based Level shifters

Comparative Analysis of Low power, high speed based Level shifters

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-53 Number-3
Year of Publication : 2017
Authors : Vaishali Kawadkar, Santosh Onker

Citation 

Vaishali Kawadkar, Santosh Onker "Comparative Analysis of Low power, high speed based Level shifters", International Journal of Engineering Trends and Technology (IJETT), V53(3),142-146 November 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Multi-VDD design reduces the power consumption in Systems-On-Chips(SoCs). As the level shifter in multi-VDD system imposes additional power consumption and propagation delay, it is necessary to optimize the level shifter circuit for minimum power-delay product (PDP) to obtain the potential benefit of using multiple power supply. Carbon nanotube FET(CNT-FET) is one of the novel devices that could replace conventional silicon MOSFET for low power applications due to its superior electrical properties. In this paper, the power and speed of CNT-FET based level shifters in 32-nm technology node are optimized by choosing chirality, diameter, number of nano tubes and substrate (back gate) bias for both feedback-based and multi-VTH based level shifters.

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Keywords
Leakage Power, CNTFET, Chirality, DCVS-LS, SI-LS, PDP, EDP.