Comparative Analysis of Performance in Domino Logic For Wide Fan-in Gates

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2018 by IJETT Journal
Volume-55 Number-2
Year of Publication : 2018
Authors : Akansha Dawda, Sher Singh
DOI :  10.14445/22315381/IJETT-V55P218


Akansha Dawda , Sher Singh "Comparative Analysis of Performance in Domino Logic For Wide Fan-in Gates", International Journal of Engineering Trends and Technology (IJETT), V55(2),94-98 January 2018. ISSN:2231-5381. published by seventh sense research group

As the in semiconductor industries progress by following Moore’s law faithfully from last five decades, and integrating more transistors along with functional circuits on a single chip periodically with every coming process technology. However, this progress help in rapid run towards tiny, circuit design high speed and economical VLSI (Very Large Scale of Integration) circuits has added to excessive power dissipation of numerous circuits used today. Therefore the leakage current and power dissipation becomes increasingly more focused in VLSI circuit design. Carbon Nanotube Field Effect Transistor (CNFETs) is suited best alternatives to the conventional CMOS based devices. During various simulation results, unexpected reduction in process variation, ultra low (nano-scaled) power memory devices and superior improvement of Noise Margin, propagation delay, write-read margin and its stability is found. CNFETs based logic gates are compared with Conventional CMOS and FinFET based logic gates in respect to delay and power consumption..

[1] J.M. Rabey, A. Chandrasekaran and B. Nicolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 2000.
[2] H.Mahmoodi, K.Roy, “Diode Footed Domino: A Leakage tolerant high fan-in dynamic circuit design style”, IEEE Trans, VLSI Syst., Vol 14, no.6, pp.646-649, Jun 2006.
[3] Farshad Moradi, Tuan Vu Cao, Elena I. Vatajelu, Ali Peiravi, Hamid Mahmoodi, Dag T. Wisland, “Domino logic designs for highperformance and leakage tolerant applications”, Integration , the VLSI journal., Vol 24, pp. 1-8, April 2012.
[4] A. Peiravi, M. Asyaei, “Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates” Integration , the VLSI journal., Vol 45, pp. 22-32, Jan 2012.
[5] F. Moradi, H. Mahmoodi, A. Peiravi, “A high speed and leakagetolerant domino logic for high fan-in gates” , in: Proceeding of the 15th ACM Great Lakes Symposium on VLSI, (GLSVLSI), Chicago, IL, USA, 2005, pp. 478–481.
[5] J.M. Rabaey, A.P. Chandrakasan, B. Nikolic, Digital Integrated Circuits, 2nd ed., Prentice Hall, Englewood Cliffs, 2003.
[6] J. Deng, H.S.P. Wong, A compact spice model for carbonnanotube field-effect transistors including non-idealities and its application – part 1: model of the intrinsic channel region, IEEE Trans. Electron Devices 54 (12) (2007) 3186–3194.
[7] A.D. Franklin, M. Luisier, S.-J. Han, G. Tulevski, C.M. Breslin, L. Gignac, et al., Sub-10 nm carbon nanotube transistor, Nano Lett. 12 (2) (2012) 758–762.
[8] Stanford CNFET Model Quick User Guide,? ?, 2014.
[9] Predictive Technology Model (PTM). 32 nm High Performance V2.1 Technology of PTM Model. (2012, Feb. 19)
[10] H. Mahmoodi and K. Roy, “Diode-footed domino: A leakagetolerant high fan-in dynamic circuit design style,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 3, pp. 495–503, Mar. 2004.
[11] A. Alvandpour, R. Krishnamurthy, K. Sourrty, and S. Y. Borkar, “A sub-130-nm conditional-keeper technique,” IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 633–638, May 2002.
[12] M. H. Anis, M. W. Allam, and M. I. Elmasry, “Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies,” IEEE Trans. Very Large Scale (VLSI) Syst., vol. 10, no. 2, 71–78, Apr. 2002

CNT, CNFET, Power Dissipation, Logic Gates.