Design of Efficient FSM Based 3D Network on Chip Architecture

Design of Efficient FSM Based 3D Network on Chip Architecture

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2020 by IJETT Journal
Volume-68 Issue-10
Year of Publication : 2020
Authors : Krutthika H.K, A R Aswatha
DOI :  10.14445/22315381/IJETT-V68I10P212

Citation 

MLA Style: Krutthika H.K, A R Aswatha  "Design of Efficient FSM Based 3D Network on Chip Architecture" International Journal of Engineering Trends and Technology 68.10(2020):67-73. 

APA Style:Krutthika H.K, A R Aswatha. Design of Efficient FSM Based 3D Network on Chip Architecture  International Journal of Engineering Trends and Technology, 68(10),67-73.

Abstract
The 3D NoC architecture is used in general Silicon on Chip (SoC) architecture to establish bidirectional communications between different processing elements which are stacked in three dimensional arrays. In the real time implementation scenarios, congestion in the network depends upon the time taken by the specific node to route and process any explicit task. Each router must be able to detect such conditions and store the data temporarily inside the respective router for further processing. In this paper, a 3D NoC router architecture is proposed which is capable to detect the congestion and process the data efficiently. The routers are vertically stacked to obtain 3D dimensional NoC structure, which intern reduces the area requirements and increases the throughput compared to traditional NoC architectures. The data format which is used in our proposed architectures has an option field for the acknowledgement at each level of data transfer which is further modeled using novel simplified FSM technique. The switching network for 3D NoC has been designed to efficiently accommodate for routing algorithm. The entire proposed architecture is modeled using FSM technique which is coded using VHDL language and implemented on Xilinx Zybo Z7-10 FPGA board. The comparison result shows that the proposed architecture is better in-terms of hardware parameters than existing methods.

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Keywords
FPGA architecture, Network On Chip, Router,System on Chip, XY Routing.