Enhanced MAC Controller Design for 2D Convolution Image Processing on FPGA

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2021 by IJETT Journal
Volume-69 Issue-9
Year of Publication : 2021
Authors : Chiranjeevi G N, Dr Subhash Kulkarni
  10.14445/22315381/IJETT-V69I9P207

MLA 

MLA Style: Chiranjeevi G N, Dr Subhash Kulkarni  "Enhanced MAC Controller Design for 2D Convolution Image Processing on FPGA" International Journal of Engineering Trends and Technology 69.9(2021):51-55. 

APA Style: Chiranjeevi G N, Dr Subhash Kulkarni. Enhanced MAC Controller Design for 2D Convolution Image Processing on FPGA  International Journal of Engineering Trends and Technology, 69(9),51-55.

Abstract
Majorities of image processing algorithms are two-dimensional (2D) and localized by their very nature. As a result, the 2D convolution function has significant implications for the requirements involving image processing. 2D Convolution and MAC design is the process used to do a variety of image analysis tasks, including picture blurring, softening, feature extraction, and image classification. The major purpose of this study is to create a more efficient MAC control block-based architecture for 2D convolution. This 2D algorithm can be implemented in hardware with a smaller number of modules, multipliers, adders, and control blocks, resulting in substantial hardware savings and reduced LUTs. Simulations were carried out in Verilog and developed and tested using Xilinx Vertex family Field Programmable Gate Arrays (FPGA) technology. In comparison to the conventional 2D convolution implementation, the recommended 2D convolution architectural technique is substantially faster and requires much fewer hardware resources.

Reference
[1] Nikhil, R. Bluespec System Verilog: Efficient, correct RTL from high-level specifications. In Proceedings of the Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE ’04), San Diego, CA, USA, 23–25 June (2004) 69–70
[2] Richard Shoup. Parameterized Convolution Filtering in a Field Programmable Gate Array Interval. Technical Report, Palo Alto, California .(1993).
[3] Hong Shan Neoh and Asher Hazanchuk, Adaptive Edge Detection for Real-Time Video Processing using FPGAs, GSPx 2004 Conference, (2004).
[4] Wang, J.; Zhong, S.; Yan, L.; Cao, Z. An Embedded System-on-Chip Architecture for Real-time Visual Detection and Matching. IEEE Trans. Circuits Syst. Video Technol., 24 (2014) 525–538.
[5] Mondal, P.; Biswal, P.K.; Banerjee, S. FPGA based accelerated 3D affine transform for real-time image processing applications. Comput. Electr. Eng. (2016).
[6] Kadric, E.; Lakata, D.; Dehon, A. Impact of Parallelism and Memory Architecture on FPGA Communication Energy. ACM Trans. Reconfigurable Technol. Syst., 9 (30) (2016) 1–30, 23
[7] Kaur, I.; Rohilla, L.; Nagpal, A.; Pandey, B.; Sharma, S. Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array. In System and Architecture; Springer: New York, NY, USA, (2018) 151–161.
[8] Pezzarossa, L.; Kristensen, A.T.; Schoeberl, M.; Sparsø, J. Using dynamic partial reconfiguration of FPGAs in real-Time systems. Micro process. Microsyst., 6 (2018) 198–206
[9] Stephen D.Brown, R.J. Francis, J.Rose, Z.G.Vranesic. Field Programmable Gate Arrays,. Shinichi Hirai, Masakazu Zakouji, Tatsuhiko Tsuboi, Implementing Image Processing Algorithms on FPGA-based Real-time Vision System, Proc. 11th Synthesis and System Integration of Mixed Information Technologies (SASIMI2003), Hiroshima, (1992) 378-385.
[10] Torres-Huitzil, C.; Nuño-Maganda, M.A. Areatime Efficient Implementation of Local Adaptive Image Thresholding in Reconfigurable Hardware. ACM SIGARCH Comput. Arch. News 42 (2014) 33–38
[11] Sungheetha, Akey, and Rajesh Sharma. A Novel CapsNet based Image Reconstruction and Regression Analysis. Journal of Innovative Image Processing (JIIP) 2(03) (2020) 156-164.
[12] Dutta, Sayantan, and Ayan Banerjee. Highly Precise Modified Blue Whale Method Framed by Blending Bat and Local Search Algorithm for the Optimality of Image Fusion Algorithm. Journal of Soft Computing Paradigm (JSCP) 2(04) (2020) 195-208.
[13] P. Lysaght, B. Blodget, J. Mason, J. Young, and B. Bridgford, Invited paper: enhanced architectures, design methodologies, and CAD tools for dynamic reconfiguration of Xilinx FPGAS, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '06) 1–6,
[14] Madrid, Spain, August 2006 Dougherty, G., Image analysis in medical imaging: recent advances in selected examples. Biomed. Imaging Interv. J. 6(3) (2010) e32,.
[15] John C. Russ, The Image Processing Handbook, 6th Edition, CRC Press, (2011).
[16] Zainalabedin Navabi, Digital Design and Implementation with Field Programmable Devices, Kluwer Academic Publishers, (2011).
[17] G. N. Chiranjeevi and S. Kulkarni, Pipeline Architecture for N=K*2L Bit Modular ALU: Case Study between Current Generation Computing and Vedic Computing, 2021 6th International Conference for Convergence in Technology (I2CT), (2021) 1-4, doi: 10.1109/I2CT51068.2021.9417917.
[18] B. S. Durgakeri and G. N. Chiranjeevi, Implementing Image Processing Algorithms using Xilinx System Generator with Real- Time Constraints, 2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT), (2019) 230-234, doi: 10.1109/RTEICT46194.2019.9016962.
[19] C. G. Narasimhamurthy and S. Kulkarni, Fast Architecture for Low- Level Vision and Image Enhancement for Reconfigurable Platform, 2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), (2021) 1-4, doi: 10.1109/ICAECT49130.2021.9392425.
[20] Chiranjeevi Gubbi Narasimhamurthy, Dr. Subhash kulkarni, Validation of the FPGA-Based Image Processing Techniques using the efficient tool like Xilinx Device Generators, International Journal of Emerging Trends in Engineering Research, doi.org/10.30534/ijeter/2021/16942021, 9(4) (2021).
[21] Y. Aoyagi and T. Asakura, A study on traffic sign recognition in scene image using genetic algorithms and neural networks, inProc. 22ndIEEE Int. Conf. Ind. Electron., Control Instrum., Taipei, Taiwan, R.O.C, 3 (1996) 1838–1843.
[22] Yiannacouras, P.; Steffan, J.G.; Rose, J. VESPA: Portable, scalable, and flexible FPGA-based vector processors. In Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, Atlanta, GA, USA, 19–24 October (2008) 61–70.
[23] Neuendorffer, S.; Li, T.; Wang, D. Accelerating OpenCV Applications with Zynq-7000 All Programmable SoC Using Vivado HLS Video Libraries; Technical Report; Xilinx Inc.: San Jose, CA, USA, (2015).
[24] So, H.K.H.; Liu, C. FPGA Overlays. In FPGAs for Software Programmers; Springer: Berlin, Germany, 2016; pp. 285–305.
[25] Kelly, C.; Siddiqui, F.M.; Bardak, B.; Woods, R. Histogram of oriented gradients front end processing: An FPGA based processor approach. In Proceedings of the 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, UK, 20–22 October (2014) 1–6.
[26] Keerti Kulkarni, Dr. P. A. Vijaya Separability Analysis of The Band Combinations For Land Cover Classification of Satellite Images, International Journal of Engineering Trends and Technology 69(8) (2021) 138-144.
[27] Srikanth Khanna, Venkatachalam Chandrasekaran, Fractional Differentiation-based Hybrid Active Contour Model for Noisy Image Segmentation, International Journal of Engineering Trends and Technology 69(8)(2021) 243-259.

Keywords
Xilinx Vertex, 2D convolution, MAC, Image processing FPGA, Image enhancement, vertex, and Zynq7000 SOC