FPGA Implementation Of VM-CSA Fir Filter With Reduced Area And Delay Using Optimal Designs

FPGA Implementation Of VM-CSA Fir Filter With Reduced Area And Delay Using Optimal Designs
  IJETT-book-cover           
  
© 2021 by IJETT Journal
Volume-69 Issue-9
Year of Publication : 2021
Authors : Arunjyothi Eddla, Dr.VY.Jayasree Pappu
DOI :  10.14445/22315381/IJETT-V69I9P224

How to Cite?

Arunjyothi Eddla, Dr.VY.Jayasree Pappu, "FPGA Implementation Of VM-CSA Fir Filter With Reduced Area And Delay Using Optimal Designs," International Journal of Engineering Trends and Technology, vol. 69, no. 9, pp. 203-211, 2021. Crossref, https://doi.org/10.14445/22315381/IJETT-V69I9P224

Abstract
Because of its various properties, such as Bounded-Input-Bounded-Output (BIBO) stability, phase linearity, and ease of implementation, the Finite Impulse Response (FIR) filter is widely employed in digital signal processing applications. High-order filters, on the other hand, need a large number of multipliers. As the number of multipliers grows, the hardware complexity and power of the FIR filter grows as well. In digital signal processing applications, the design of the low area and low power FIR filters is critical. To reduce hardware consumption, an essential form of FIR filter called the Interpolated Spectral Parameter Approximation (ISPA) filter is introduced in this study. To reduce the number of logical components in the ISPA filter, the Carry SKIP Adder (CSA) and Vedic Multiplier (VM) are combined. Furthermore, raising the ISPA filter`s working frequency reduces the ISPA filter`s latency. The Parks-McClellan algorithm will be used to create the coefficient. The ISPA filter, as well as the optimum adder and multiplier, are implemented using Modelsim 10.5 and Xilinx 14.4. The suggested ISPA filter`s performance is evaluated in terms of filter output, LUT, flip flops, slices, power, and delay.

Keywords
Carry Look Ahead adder, Finite Impulse Response, Interpolated Spectral Parameter Approximation, Parks-McClellan, and Vedic Multiplier

Reference
[1] Park, Sang Yoon, and Pramod Kumar Meher., Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter., IEEE Transactions on Circuits and Systems II: Express Briefs 61(7) (2014) 511-515.
[2] Thakur, Rakhi, and KavitaKhare., High-speed FPGA implementation of FIR filter for DSP applications., International Journal of Modeling and Optimization 3 (1) (2013) 92-94.
[3] Badave, S. M., and A. S. Bhalchandra., Multiplierless fir filter implementation on fpga., International Journal of Information and Electronics Engineering 2(2) (2012) 185.
[4] Ryou, Albert, and Jonathan Simon., Active cancellation of acoustical resonances with an FPGA FIR filter., Review of Scientific Instruments 88, no. 1 (2017): 013101.
[5] Bhattacharjee, Subhankar, SanjibSil, and AmlanChakrabarti., Evaluation of power-efficient FIR filter for FPGA based DSP applications., Procedia Technology 10 (2013) 856-865.
[6] Lehto, Raija, TarjaTaurén, and Olli Vainio., Recursive FIR filter structures on FPGA., Microprocessors and Microsystems 35(7) (2011) 595-602.
[7] Singh, Gurpadam, and Neelam R. Prakash., FPGA Implementation of Higher Order FIR Filter., International Journal of Electrical and Computer Engineering 7(4) (2017) 1874.
[8] Keerthi, M., VasujadeviMidasala, and S. NagakishoreBhavanam., FPGA implementation of distributed arithmetic for fIR filter., International Journal of Engineering Research and Technology 1(9) (2012).
[9] Szadkowski, Zbigniew, D. G?as, C. Timmermans, and T. Wijnen., First results from the FPGA/NIOS adaptive FIR filter using linear prediction implemented in the auger engineering radio array., IEEE Transactions on Nuclear Science 62(3) (2015) 977-984.
[10] Pandey, Bishwajeet, Bhagwan Das, Amanpreet Kaur, Tanesh Kumar, Abdul Moid Khan, DM Akbar Hussain, and Geetam Singh Tomar., Performance evaluation of FIR filter after implementation on different FPGA and SOC and its utilization in communication and network., Wireless Personal Communications 95(2) (2017) 375-389.
[11] Kalaiyarasi, D. and Reddy, T.K., Design and implementation of least mean square adaptive FIR filter using offset binary coding-based distributed arithmetic. Microprocessors and microsystems, 71(2019) 102884.
[12] Prasad, J., Geetha, D.M. and Srinivasan, K., Experimental setup of stretchable arid dry pad sensors for the signal acquisition fir filter design using Vedic approach. Measurement, 141(2019) 209-216.
[13] Diaz, C., Sanchez, G., Avalos, J.G., Sanchez, G., Sanchez, J.C. and Perez, H., Spike-based compact digital neuromorphic architecture for efficient implementation of high order FIR filters. Neurocomputing, 251(2017) 90-98.
[14] Sundar, P.P., Ranjith, D., Karthikeyan, T., Kumar, V.V., and Jeyakumar, B., Low power area-efficient adaptive FIR filter for hearing aids using distributed arithmetic architecture. International Journal of Speech Technology, (2020) 1-10.
[15] Roy, S. and Chandra, A., On the Order Minimization of Interpolated Bandpass Method Based Narrow Transition Band FIR Filter Design. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(11) (2019) 4287-4295.
[16] Samyuktha, S and Chaitanya, D.L., VLSI design of efficient FIR filters using Vedic Mathematics and Ripple Carry Adder, Material today proceedings., (2020).
[17] Bharat Garg and Sujit Kumar Patel., Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency, Journal of Signal Processing Systems., (2020).
[18] SILVIU-IOAN FLIP., A Robust and Scalable Implementation of the Parks-McClellan Algorithm for Designing FIR Filters, ACM Transactions, (2016) 24.
[19] Blok, M., April. Farrow structure implementation of fractional delay filter optimal in Chebyshev sense. In Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments., 6159(4) (2016) 61594. International Society for Optics and Photonics.
[20] Singh, A., Dhillon, N., and Bains, S.S., FIR Filter Design With Farrow Structure Using Genetic Algorithm.International Journal of Computer & Organization Trends 3(9) (2013).