Robust Schmitt Trigger-based Performance Booster Technique for Futuristic On-Chip Graphene Interconnects

Robust Schmitt Trigger-based Performance Booster Technique for Futuristic On-Chip Graphene Interconnects
  IJETT-book-cover           
  
© 2022 by IJETT Journal
Volume-70 Issue-3
Year of Publication : 2022
Authors : Urmi Shah, Usha Mehta
https://doi.org/10.14445/22315381/IJETT-V70I3P227

How to Cite?

Urmi Shah, Usha Mehta, "Robust Schmitt Trigger-based Performance Booster Technique for Futuristic On-Chip Graphene Interconnects," International Journal of Engineering Trends and Technology, vol. 70, no. 3, pp. 241-248, 2022. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I3P227

Abstract
For compactly high-speed and dense nanoscale integrated circuits (ICs), it is essentially on-chip interconnects rather compared to the devices that govern the performance of the chip. At nanometer-regime, the performance of existing widely used copper on-chip interconnect is adversely affected by varying limiting effects such as sidewall and grain boundaries scatterings. Subsequently, efficient and prospective graphene is investigated as one of the most promising contenders for on-chip interconnect materials. One of the most common strategies for addressing on-chip signal deterioration caused by long interconnects is repeater insertion. CMOS inverter-based buffer has been proposed as a prominent repeater circuit by many researchers. However, these conventional buffers have a high switching time that cumulatively adds up the overall signal delay. To mitigate this issue, a novel CMOS Schmitt trigger-based booster for contemporary futuristic graphene-based nanowires has been proposed in the present paper so as to attain better signal restoration, lesser delay and power reduction. The several analyses performed in this paper show that graphene interconnects with Schmitt trigger gives on average 45% of speed improvement and average power reduction of 40% with respect to conventional CMOS inverter-based buffer design. Also, the efficiency of Schmitt trigger circuits has been verified at varying different technology nodes.

Keywords
Copper interconnects, Graphene interconnects, Repeater Insertion, Schmitt Trigger, VLSI technology.

Reference
[1] (2012). International Technology Roadmap for Semiconductors (ITRS). Update. [Online]. Available: www.itrs.net/.
[2] J. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Design (Berkely: Pearson) (1995).
[3] S. Saini, A. Mahesh and S. Veeramachaneni, An Alternative Approach to Buffer Insertion for the Delay and Power Reduction in VLSI Interconnect, In Proc. 23rd IEEE Int. Conf. on VLSI Design. (2010).
[4] B. Kaushik, V. Ramesh and A. Patnaik, Crosstalk in Modern On-Chip Interconnects- A FDTD Approach, Springer Briefs in Applied Sciences and Technology, Springer. (2016).
[5] M. Rail, A. Chatterjee, S. Sarkar and B. Kaushik, Performance Analysis of Multilayer Graphene Nanoribbon (MLGNR) Interconnects, IEEE Trans. on Computational Electronics. 15 (2016) 358–366.
[6] Y. Agrawal, M. Girish and R. Chandel, A Novel Unified Model for Copper and MLGNR Interconnects Using Voltage and Current Mode Signalling Schemes, IEEE Transaction on Electromagnetic Compatibility. 59 (2017) 217-221.
[7] A. Naeemi and J. Meindl, Compact Physics-Based Circuit Models for Graphene Nanoribbon, Interconnects, IEEE Trans. on Electron Devices. 56 (2009) 1822 – 1833.
[8] L. Liu, Y. Zhou and S. Hu, Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing Optimization, In Proc. IEEE Computer Society Annual Symposium on VLSI. (2014) 362-367.
[9] B. Kaushik, S. Goel and G. Rauthan, Future VLSI Interconnects Optical Fiber or Carbon Nanotube - A Review, Microelectronics International. 24 (2007) 53-63.
[10] A. Naeemi and M. Meindl, Conductance Modelling for Graphene Nanoribbon (GNR) Interconnect Electron Device Letter. 28 (2007) 428–431.
[11] M. Tang and J. Mao, Wire Sizing Optimization for Buffered Global Interconnects, In Proc. Int. Conf. on Microwave and Millimetre Wave Technology. 2 (2003) 479-482.
[12] R. Alaa and F. Yuan, A New Simple RC Modelling for On-Chip Interconnect with its Applications to Buffer Insertion, In Proc. Saudi Int. Conf. on Electronics Communications and Photonics. (2013).
[13] D. Patel and B. Kim, Carbon Nanotube Bundle Interconnect Performance Evaluation Optimum Repeater Size and Insertion for Global Wire, In Proc. 53rd IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS). (2010) 749-752.
[14] C. Alpert and A. Devgan, Wire Segmenting for Improved Buffer Insertion, In Proc. IEEE/ACM Design Automation Conf. (1997) 588–593.
[15] Y. Agrawal, G. Mekala and R. Chandel, Comprehensive Model for High-Speed Current-Mode Signalling in Next-Generation MWCNT Bundle Interconnect Using FDTD Technique, IEEE Trans. on Nanotechnology. 15 (2016) 590-598.
[16] A. Kahng, S. Muddu and E. Sarto, Interconnect Optimization Strategies for High-Performance VLSI Designs, In Proc. Int. Conference on VLSI Design. (1999).
[17] K. Reddy et al., Delay Uncertainty in MLGNR Interconnects Under Process-Induced Variations of Width, Doping, Dielectric Thickness and Mean Free Path, Journal of Computational Electronics. (2014) 225-226.
[18] S. Nasiri and R. Faez, Compact Formulae for the Number of Conduction Channels in Various Types of Graphene Nanoribbons at Various Temperatures, Modern Physics Lett. 26 (2012).
[19] U. Shah and U. Mehta, Assessing Effect of Variability in Nano-Scale On-Chip Interconnects, In Proc. of Advances in VLSI and Embedded System, Springer. (2021).
[20] S. Kundra and P. Soni, Low Power Schmitt Trigger Innovative Systems Design and Engineering. 3 (2) (2012) 2222-1727.
[21] N. Patel and Y. Agrawal, A Literature Review on Next-Generation Graphene Interconnects, Journal of Circuits Systems, and Computers. 28(9) (2019).
[22] T. Parade, U. Shah, Y. Agrawal and R. Parekh, Preeminent Buffer Insertion Technique for Long Advanced On-Chip Graphene Interconnects, in Proc IEEE Electrical Design of Advanced Packaging and System. (2018) 1-3.
[23] C. Xu, H. Li, and K. Banerjee, Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnect, IEEE Trans. on Electron Devices. 56 (2009) 1567-1578.
[24] H. Li, C. Xu, N. Srivastava, and K. Banerjee, Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects, IEEE Trans. on Electron Devices. 56 (9) (2009) 1799-1821.
[25] N. Patel, Y. Agrawal, A Literature Review on Next-Generation Graphene Interconnects, Journal of Circuits, Systems, and Computers. 27(9) (2018).
[26] X. Wang, Fabrication of Ultralong and Electrically Uniform Single-Walled Carbon Nanotubes on Clean Substrates, Nano Electronics Lett. 9 (2009) 3137–3141.
[27] M. Tiang and J. Mao, Modeling and Fast Simulation of Multiwalled Carbon Nanotube Interconnect, IEEE Trans. on Electromagnetic Compatibility. 57 (2015) 232-240.