Hybrid State Analysis with Predictive Model Control on Memory Controller using Machine Learning Algorithms

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2022 by IJETT Journal
Volume-70 Issue-4
Year of Publication : 2022
Authors : Vijayalakshmi ch, Jaikaran Singh
  10.14445/22315381/IJETT-V70I4P231

MLA 

MLA Style: Vijayalakshmi ch, and Jaikaran Singh. "Hybrid State Analysis with Predictive Model Control on Memory Controller using Machine Learning Algorithms." International Journal of Engineering Trends and Technology, vol. 70, no. 4, Apr. 2022, pp. 360-372. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I4P231

APA Style: Vijayalakshmi ch, & Jaikaran Singh.(2022). Hybrid State Analysis with Predictive Model Control on Memory Controller using Machine Learning Algorithms. International Journal of Engineering Trends and Technology, 70(4), 360-372. https://doi.org/10.14445/22315381/IJETT-V70I4P231

Abstract
The design perspective of the memories and their implementation have become computational storage for all the different scenarios of applications governed by the current AI market. The feature of low latency devices or hardware for the application on Mobiles, laptops, etc., is implicated with AI technology with improved memory control and power modules encapsulating the output performance. One such model and structural changes have been implemented with the Hybrid model on low latencies with probabilities, also the memory bandwidth of the proposed controller and memory unit utilized in Wireless applications. With the feature of Area, power, and delay, our Design investigates the feature of reliability of the data storage on the memory model and its formulation approach for low latency. An intuitive approach to gate-level Design with flash memories is implicated with predictive memory array structures for the low area and power efficiency.

Keywords
Built-in self-test (BIST), Computational Memory Architecture (CMA), Design for testability (DFT).Fieldprogrammable gate array (FPGA), Processing Elements (PEs).

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