Area Efficient Moving Object Detection using Spatial and Temporal Method in FPGA

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2022 by IJETT Journal
Volume-70 Issue-9
Year of Publication : 2022
Authors : Sudhir Dagar, Geeta Nijhawan
DOI : 10.14445/22315381/IJETT-V70I9P214

How to Cite?

Sudhir Dagar, Geeta Nijhawan, "Area Efficient Moving Object Detection using Spatial and Temporal Method in FPGA," International Journal of Engineering Trends and Technology, vol. 70, no. 9, pp. 138-147, 2022. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I9P214

Abstract
Background subtraction has become a challenging task for moving objects. Mainly its complexity of implementation at moving background. Area Efficient hardware implementation of a moving object detection algorithm using FPGAs is described in this paper. The algorithm aims to remove moving items' backgrounds from the CDNet dataset. Even though occlusions aren't detected, simple shadow and highlight reduction are performed. The technique is best implemented on pipelined technology and is optimized for high frame rates. The authors proposed unique improvements, such as background binary mask combinations or non-linear functions in highlight detection, which improved the resiliency and efficiency of hardware implementations. After being developed in FPGA, the method was tested on the CDNet dataset.

Keywords
Binary Mask, BS, CDNet, FPGA, GMM, etc.

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