An Efficient Carry Select Adder with Less Delay and Reduced Area Application
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2013 by IJETT Journal|
|Year of Publication : 2013|
|Authors : Pandu Ranga Rao , Priyanka Halle|
Pandu Ranga Rao , Priyanka Halle. "An Efficient Carry Select Adder with Less Delay and Reduced Area Application ". International Journal of Engineering Trends and Technology (IJETT). V4(9):3766-3770 Sep 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group.
Design of area, high speed and power - efficient data path logic systems forms the largest areas of research in VLSI system design. The addition speed is limited by the time necessary to transmit a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in several data - processing processors to p erform fast arithmetic purpose . From the configuration of the CSLA, it is clear that there is scope for decreasing the area and delay in the CSLA. This work uses a simple and an efficient gate - level modificat ion which drastically reduces the area and delay of the CSLA. Based on this modification 16, 32, 64 and 128 - bit square - root Carry Select Adder (SQRT C SLA) architectures have been improved and compared with the regular SQRT CSLA architecture. The proposed design has compact area and delay to a great extent when compared with the regular SQRT CSLA. This work estimates the performance of the planned designs with the regular designs in terms of delay, area and synthesis are implemented in Xilinx FPGA. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
 Bedrij, O. J., (1962), “Carry - select adder,” IRE Trans. Electron. Comput. Pp.340 – 344.
 Ramkumar,B. , Kittur, H.M. and Kannan ,P. M.,(2010 ),“ASIC implementation of modified faster carry save adder,” Eur. J. Sci. Res., vol. 42, no. 1,pp.53 – 58.
 Kim ,Y. and Kim ,L. - S.,(May2001), “64 - bit carry - select adder with reduced area, “Electron Lett., vol. 37, no. 10, pp. 614 – 615.
 Ceiang, T. Y. and Hsiao. J., (Oct 1998), “Carry - select adder using single ripple carry adder,” Electron. Lett., v ol. 34, no. 22, pp. 2101 – 2103
 He, Y., Chang, C. H. and Gu, J., (2005), “An A rea efficient 64 - bit square root carry - select adder for low power application,” in Proc. IEEE Int. Symp.Circuits Syst. vol. 4, pp. 4082 – 4085.
 E. Abu - Shama and M. Bayoumi, “A New cell for low power adders,” in Proc.Int.Midwest Symp. Circuits and Systems, 1995, pp. 1014 – 1017
 Samir Palnitkar, “Verilog Hdl, A guide to Digital Design and Synthesis ”
(ASIC), area - efficient, CSLA, low delay.