Design Approach for Decimation Filter for ADC Application

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-10 Number-12
Year of Publication : 2014
Authors : Gautam G. Moon , Prof. Sonali N. Joshi


Gautam G. Moon , Prof. Sonali N. Joshi. "Design Approach for Decimation Filter for ADC Application", International Journal of Engineering Trends and Technology (IJETT), V10(12),597-600 April 2014. ISSN:2231-5381. published by seventh sense research group


This paper presents a kind of design method about the decimation filter design for high performance ADC application. It was implemented and validated by simulation using MATLAB tool and its complete architecture was realized using DSP blockset and Simulink. A two-stage decimation filter architecture which can reduce digital switching noise was also introduced in this design. The FIR low pass filter is used for both the stages of the decimation filter as a anti-aliasing filtering process. The resulting architecture having increased computational efficiency, smaller size and high performance also it consumes less power as compared to conventional decimation filters. The design was simulated using MATLAB according to this scheme can achieve higher performances.


[1] Li Hongqin “Digital Decimation Filter Design and simulation for Delta-Sigma ADC with High Performance” 2007 IEEE, pp. 922-925.
[2] Khalid H. Abed, Shailesh B. Nerurkar , Stephen Colaco “Design and Implementation of a Decimation Filter For High Performance Audio Applications” 2007 IEEE, pp. 812-815.
[3] K. Shunhagavalli, Dr. P. Vanaiaranian, “An Area Optimization of Decimation Filter Using CSD Representation For Hearing Aid Application” ISSC 2006, pp. 303-307.
[4] Khalid H. Abed, Shailesh B. Nerurkar, “Low Power and Hardware Efficient Decimation Filter” 2003IEEE, pp. 454-459.
[5] Yonghao Wang, and Joshua Reiss “Time Domain Performance of Decimation Filter Architectures for High Resolution Sigma Delta Analogue to Digital Conversion” AES 132nd Convention paper 2012, April 26–29.
[6] Tanee Demeechai, Siwaruk Siwamogsatham, “A New Architecture for Decimating FIR Filter” International Journal of Hybrid Information Technology Vol. 5, No. 2, April 2012, pp. 109-116.
[7] Yingying Cui, Jie Huang, Lingjuan Wu, “An Optimized Design for a Decimation Filter and Implementation for Sigma-Delta ADC” 2009.
[8] “Digital Signal Processing” Principles, Algorithms and Applications” -John G. Proakis, Dimitris G. Manolakis Prentice-Hall India.

Digital Decimation Filter, ADC, FIR low pass filter, Comparator.