Design and Analysis of a Floating Point Fused Multiply Add Unit using VHDL

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2015 by IJETT Journal
Volume-24 Number-4
Year of Publication : 2015
Authors : Farouq Aliyu
DOI :  10.14445/22315381/IJETT-V24P232

Citation 

Farouq Aliyu"Design and Analysis of a Floating Point Fused Multiply Add Unit using VHDL", International Journal of Engineering Trends and Technology (IJETT), V24(4),169-176 June 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Ever since the growth of processing speed began to slow down due to immense heat generated by the processing units, engineers started looking for other speed up alternatives. One of such is the ”Fuse Multiply Add” (FMA) unit. This unit combines multiplication of two operands and their summation with third operand as a single instruction. As a result, a floating point primitive is created out of the two arithmetic operations. This paper describes the design and development of a FMA. It also points out the limitations of the FMA using VHDL programming language. Furthermore, the paper points the mechanics of the different parts of the FMA in order to shade more light on those parts of the FMA that prove costly in terms of speed, power and area.

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Keywords
Computer Arithmetic, Fused Multiply-Add, FMA, IEEE Floating-point, Leading Zero Detector, Leading Zero Anticipator.