Design Low-Power Pulse-Triggered Flip-Flop using 90 nm CMOS Technology
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2015 by IJETT Journal|
|Year of Publication : 2015|
|Authors : B. Sudheer Kumar, M. Venkata Sreeraj
B. Sudheer Kumar, M. Venkata Sreeraj"Design Low-Power Pulse-Triggered Flip-Flop using 90 nm CMOS Technology", International Journal of Engineering Trends and Technology (IJETT), V30(3),128-132 December 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
VLSI Design analysis of three important considerations is power, area and delay. Flip-flop is one of the most power consumption components. As the power budget of today’s portable digital circuits is severely limited. It is important to reduce the power dissipation in both clock distribution networks and Latch design. Pulse generation Control logic design of the Flip Flop is reduce the power compare to other Flip Flop. In this paper, we present a pulsed triggered Flip-Flop design based on a novel pulse generator circuit. Our design achieves significantly improved speed when compared to recent pulsed Flip-Flop design, as well as a Existing Flip Flops. We are going to design a compare various type of flip flops & its effect of this clocking system & compare their power consumption & to create a new design using this clocking system.
 Low-Power Pulse-Triggered Flip-Flop esign Based on a
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Flip-flop, Low power, Pulse-triggered.