Reconfigurable Fir Digital Filter Realization on FPGA

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2015 by IJETT Journal
Volume-30 Number-3
Year of Publication : 2015
Authors : Atmakuri Vasavi, Sita Madhuri Bondila


Atmakuri Vasavi, Sita Madhuri Bondila"Reconfigurable Fir Digital Filter Realization on FPGA", International Journal of Engineering Trends and Technology (IJETT), V30(3),133-137 December 2015. ISSN:2231-5381. published by seventh sense research group

This paper presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite-impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM and the RAM-based LUT is found to be costly for ASIC implementation. Therefore, a shared-LUT design is proposed to realize the DA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage. The proposed design has nearly 68% and 58% less area-delay product and 78% and 59% less energy per sample than the DA-based systolic structure and the carry save adder (CSA)-based structure, respectively, for the ASIC implementation. A LUT, which stands for LookUp Table, in general terms is basically a table that determines what the output is for any given input(s). In the context of combinational logic, it is the truth table. This truth table effectively defines how your combinatorial logic behaves.In other words, whatever behaviour you get by interconnecting any number of gates (like AND, NOR, etc.), without feedback paths (to ensure it is state-less), can be implemented by a LUT.


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FIR, Digital Filter, Reconfigurable, FPGA.