Comparative Analysis of Domino Logic Circuits for Better Noise and Delay Performance

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2015 by IJETT Journal
Volume-30 Number-3
Year of Publication : 2015
Authors : Ankit Kori, Mohammed Arif
DOI :  10.14445/22315381/IJETT-V30P225


Ankit Kori, Mohammed Arif"Comparative Analysis of Domino Logic Circuits for Better Noise and Delay Performance", International Journal of Engineering Trends and Technology (IJETT), V30(3),138-141 December 2015. ISSN:2231-5381. published by seventh sense research group

High speed and lower power consumption are the most important aspects in microprocessors as the technology curtails. Dynamic logic technique is preferred over static logic technique for the higher performance circuit due to its faster speed and lesser area overhead. In this paper we compare the power and delay for the various domino circuits provided with 8-bit, comparison of power, delay, and unit noise gain (UNG) of different topologies. The simulation is performed in Cadence Virtuoso at 90nm and 65nm process technology with supply voltage 1V and 0.9V, operating temperature of 27? C for fair comparison of results.


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Domino Logic, High speed, Low power, UNG.