Design and Simulation of SRAM to Reduce Leakage Current using Enhanced Galeor Approach
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2016 by IJETT Journal|
|Year of Publication : 2016|
|Authors : Anitha.K, Darwin.S, Mangala MariSelvi.E, Vijayalakshmi.K
|DOI : 10.14445/22315381/IJETT-V32P264|
Anitha.K, Darwin.S, Mangala MariSelvi.E, Vijayalakshmi.K"Design and Simulation of SRAM to Reduce Leakage Current using Enhanced Galeor Approach", International Journal of Engineering Trends and Technology (IJETT), V32(7),338-342 February 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In this VLSI design era, low power memory is a need of all computing devices with high performance. The power is most important aspect for today’s technology. So design a memory with low power is a vital role. With the rapid progress of technology development, threshold voltage is scale down very narrowly i.e., 180nM from 22nM. Reducing threshold voltage is the major cause of occurring leakage current in SRAM architecture. Enhanced GAted LEakage transistOR (EGALEOR) is a novel technique presented in this paper to reduce leakage current in SRAM architecture. The proposed technique will reduce 40% of static (leakage) power in write operation and 43% of static (leakage) power in read operation. This technique is designed and simulated in Tanner Software.
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Leakage current, 6T SRAM, threshold voltage, GALEOR and KGALEOR.