Impact Analysis of DGMOSFET using High-k Dielectric material

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-34 Number-4
Year of Publication : 2016
Authors : Rajesh Kumar, Rajesh Mehra
DOI :  10.14445/22315381/IJETT-V34P237


Rajesh Kumar, Rajesh Mehra "Impact Analysis of DGMOSFET using High-k Dielectric material", International Journal of Engineering Trends and Technology (IJETT), V34(4),179-183 April 2016. ISSN:2231-5381. published by seventh sense research group

Scaling of MOSFET Devices is an important factor in the advancement of Silicon Technology. This paper examines the Performance Evaluation of a DG MOSFET Devices in the presence of High-k dielectric material like HfO2, ZrO2 as compare to conventional bulk SiO2. A New device structure known as DG MOSFET is simulated, discussed and its efficiency in suppressing short channel effects (SCEs) like Threshold voltage, Leakage current(Ioff), Drain induced barrier lowering(DIBL),Sub-threshold-slope(SS) has been analyzed. It is observed that using High-k dielectric material HfO2, ZrO2 there is decrease in leakage current of about 14% in HfO2 and 25% in ZrO2 having LG of 25nm has been observed as compare to conventional Bulk SiO2 material. Also, there is significant decrease in Sub-threshold slope is observed about 46% in HfO2 , 96% in ZrO2 with LG=24nm and 141% in HfO2 ,172% in ZrO2 with LG=12nm as compared to SiO2.


[1].Y.K. Choi, K. Asano, N.Lindert, V. Subramanian, T.J King, J.Bokor, and C.Hu, “Ultrathin-body SOI MOSFET for Deep-Sub-Length Micron Era,”IEEE Electron Device letters, Vol 21, No.5, pp.254,2000.
[2] K.Uchida, H.Watanabe, a. Kinoshita,J.Koga, T.Numata, and S.I.Takagi, “Experimental study on carrier transport mechanism in ultrathin body SOI n and p MOSFETs with SOI Thickness less than 5 nm”, IEEE Electron Devices Magazine Tech. Dig., pp. 47,2002
[3] International Technology roadmap for semiconductors, 2009,online
[4] D.Sharma,R.Mehra, “Low Power,Delay Optimized Buffer Design using 70nm CMOS Technology” , International Journal of Computer Applications, Vol.22,No.3,pp.13-18, 2011.
[5] Alok Kushwaha,M.K Pandey, S.Pandeyand A.K Gupta, “Analysis of 1/f Noise in n-channel Double-Gate Fully- Depleted SOI MOSFET in n-Channel Double-Gate Fully- Depleted SOI MOSFET” International Journal Of Semiconductor Technology and science,Vol.5, No.3, pp.187-194, Sept. 2005
[6] Tsood,R.Mehra, “Design a Low Power Half Subtarctor Using 90?m CMOS Technology” , IOSR Journal of VLSI and Signal Processing,Vol.2,No.3,pp.51-56,2013.
[7] H.C. Poon, L.D. Yau, R.L. Johnston, and D. Beecgam, “DC Model for short-channel IGFET’s,” in IEDM Tech. Dig.,pp.156-159,1974
[8] Jean-Pierre Colinge, “Silicon-on-insulator Technology: Materials to VLSI”, 2nd Edition , Kluwer, 1997.
[9] K.K.Young, “Short-channel effect in Fully Depleted SOI MOSFETs”, IEEE Transactions on Electron Devices, Vol.36, No.2,pp.3 99-402, Jan1989.
[10] T.Tsuchiya, Y.Sato, M.Tomizawa,“Three Mechanisms determining short-channel effects in fully-depleted SOI MOSFETs”,IEEE Transactions on Electron Devices, Vol.45,No.5,PP.1116-1121,1998.
[11] B. Yu,H.Wann, A.Joshi, Q.Xiang, E.Ibok, and M.R.Lin, “15nm Gate Length Planar CMOS Transistor,” in Int. Electron Devices Meeting Tech. Dig. Pp. 937-939, 2001.
[12] D. Rechem, S.Latreche and C.Gontrand, “Channel Length Scaling and the Impact of Metal Gate Work Function on the Performance of Double Gate-Metal Oxide Semiconductor Field-effect Transistors”, Pramana J. Phys. Vol.72,No.3, Mrach 2009.
[13] D.M. Caughey, R.E.Thomas, “Carrier Mobilities in Silicon Emperically Related to Doping and Field”, IEEE Trans. Electron Devices, Vol.55,issue:12,pp.2192- 2193,Dec.1967.
[14]K.Cherkaoui, S.Monaghan, M.A. Negara, M.Modreanu, P.K. Hurley, D.O’Connell, S.McDonnell,G. Hughes, “Electrical, Structural, and chemical properties of HfO2 films formed by electron beam evaporation” , Journal of Applied Physics, Vol.104, No.6,Oct. 2008.
[15]V.R Chinchamalatpure, S.M. Chore, S.S. Patil, G.N. Chaudhari, International Journal of Modern Physics,Vol.3,pp.69-73,2012
[16]Slimani Samia, djellouli Bouaza, “High Dielectric Permitivity Impact On SOI Double Gate MOSFET”, International Journal Of Microelectronics Engineering, Vol.32, pp.213-219, April 2013.
[17] J.L. Ajay, M.Hirose, International Journal of applied Physics ,Vol.81,pp.1606, 1997.
[18] S.Miyazaki, “Photoemission Study Of Energy Band Alignments and Gap State Density Distributions For High-k Gate Diectrics” J. Vac. Sci. Technol. Vol. B19, No.6, pp.2212-2216, 2001.
[19] S.Sayan , E.Garfunkel, and S. Suzer, Applied Physics Letters, Vol. 80, pp.2135-2137,2002.
[20] V.V. Afanasev, M.Houssa, S. Stesmans, Journal of Applied Physics, Vol.91,pp.3079, 2002
[21] S. Slimani, B.Djellouli, “The Impact of High dielectric Permitiviy of 2-D numerical modeling nanoscale SOI Double-Gate Mosfet using Nextnano simulator ,International Conference on Advances in Circuits, Electronics and Micro-electronics,pp.38-41, August 21,2011.

Dielectric, High-k, MOSFET, Scaling, SCEs, Leakage, DIBL, SS.