A Survey on Leakage Reduction on Logic Gate in Deep Submicron Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-35 Number-5
Year of Publication : 2016
Authors : Md Tauseef, Sudeep Sharma, Rita Jain
DOI :  10.14445/22315381/IJETT-V35P249


Md Tauseef, Sudeep Sharma, Rita Jain"A Survey on Leakage Reduction on Logic Gate in Deep Submicron Technology", International Journal of Engineering Trends and Technology (IJETT), V35(5),228-232 May 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

The popularity and necessity of portable electronic systems by users have strongly influenced VLSI designers to make great effort for reduced silicon area, improved speeds, long duration battery life, and great reliability. The VLSI designers always try to save power consumption while designing a system. The performance of circuit is strongly influenced by the choice of logic style to design the digital circuit. Design optimization at circuit level is very important to avoid any degradation in output voltage level, to achieve less power consumption, to have less propagation delay in critical path and to be reliable at reduced supply voltage as we scale down towards deep sub micron technology. Switching activity of circuit affects the dynamic power consumption but with the technology scaling, the number of transistors is continuously reduced which increases the static leakage power at lower supply voltage. In a few technology generations, leakage power is supposed to become a main contributor of total power consumption. In this Paper we calculate impact of leakage power on conventional gate at 45nm and 32nm technology by using HSPICE simulator at supply voltage of 0.9V and 1V with 250C and 1000C at 10MHz frequency.


[1] K.Roy and S.C. Prasad, “Low-power CMOS VLSI circuits design”. New York: Wiley, 2000, ch.5, pp.214-219.
[2] Y.Taur, T.H. Ning, “Fundamentals of Modern VLSI Devices”, Cambridge University Press, New York, 1998.
[3] International Technology Roadmap for Semiconductors (ITRS- ).http://www.itrs.net/Links/2005ITRS/Design2005.pdf.
[4] Ali Peiravi, Mohammad Asyaei.” Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates” INTEGRATION, the VLSI Journal 45 (2012), pp 22–32.
[5] K. Roy, S.Mukhopadhyay, H. Mahmoodi-meimand, “Leakage tolerant mechan- isms and leakage reduction techniques in deepsubmicron CMOS circuits”, Proceedings of the IEEE 91 (2003), pp. 305–327.
[6] M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, “Gated-Vdd: A Circuit Techniqueto Reduce Leakage in Deep submicron Cache Memories,” International Symposium on Low Power Electronics and Design, July 2000, pp. 90-95.
[7] Z. Chen, M. Johnson, L. Wei and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks,” International Symposium on Low Power Electronics and Design, August 1998, pp. 239-244.
[8] Kawaguchi, H., Nose, K., and Sakurai, T. “ A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Pico ampere Stand-By Current,” IEEE Journal of Solid State Circuits vol.35,n.10, October 2000, pp.1498-1501.
[9] Se Hun Kim, Vincent J. Mooney III, “Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design”
[10] A. Chandrakasan, I. Yang, C. Vieri, and D. Antoniadis, Design Considerations and Tools for Low- Voltage Digital System Design," In Proceedings of the 33rd Design Automation Conference, pp. 113{118, 1996}.
[11] J. Kao, A. Chandrakasan, and D. Antoniadis, Transistor Sizing Issues and Tools for Multi-threshold CMOS Technology," In Proceedings of the 34th Design Automation Conference, pp. 409{414, Las Vegas, Nevada, 1997}.
[12] A. Chandrakasan, J. Kao "MTCMOS sequential circuits, “Proceedings of European Solid-State Circuits Conference, September 2001,pp 332- 335.
[13] Park, J. C., and Mooney III, V. J. “ Sleepy Stack Leakage Reduction,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 14, Nov 2006, pp.1250-1263.
[14] S. Kim and V. Mooney, “The Sleepy Keeper Approach: Methodology, Layout and Power Results for a 4 bit Adder,” Technical Report GITCERCS-06- 03, Georgia Institute of Technology, March 2006,

Leakage Power, Subthreshold Current, Gate oxide Current, Shorter channel Effect.