A drowsy cache method based 6T SRAM cell with different performance parameter at 32 nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-42 Number-8
Year of Publication : 2016
Authors : Garima Upadhyay, Amit Singh Rajput, Nikhil Saxena
DOI :  10.14445/22315381/IJETT-V42P271


Garima Upadhyay, Amit Singh Rajput, Nikhil Saxena "A drowsy cache method based 6T SRAM cell with different performance parameter at 32 nm Technology", International Journal of Engineering Trends and Technology (IJETT), V42(8),411-415 December 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Now a day, speedy growth of portable or hardly applications are need of technology. These hardly applications bounded the static random access memory (SRAM) topologies to consider about low leakage current and reduce power consumption. To reduce leakage current and enhance stability many topologies proposed in conventional 6T SRAM cell. This paper presents a drowsy cache method in conventional 6T SRAM cell to boost cell performance at 0.9V power supply. In this paper, we propose a method to achieve 8x and 6x time enhancement in leakage current and power dissipation respectively compare to conventional 6T SRAM cell. Simulations results are improved in read stability read/ write delay, ION/IOFF, leakage current and power dissipation using 32 nm technologies.


[1] S. Rathore, A. Prof, V. Yadav, and R. Jain, “A Brief Review of SRAM Architecture with Various Low leakage Power Reduction Technique in Recent CMOS Circuit,” International Journal for Research in Applied Science & Engineering Technology (IJRASET), vol. 3, no. I, pp. 114–120, 2015.
[2] A. C. S. Cell, “Design and Stability Analysis of CNTFET based SRAM Cell,” Conference on Electrical, Electronics and Computer Science, 2016.
[3] M. Samson, “Stable and Low Power 6T SRAM,” International Journal of Computer Applications, vol. 78, no. 2, pp. 6–10, 2013.
[4] P. K. Rajak, S. N. Singh, A. K. Rajak, and S. K. Kankanala, “Low Leakage and High Density 4T CMOS SRAM in 45nm Technology,” International Journal of Technology Innovations and Research (IJTIR), vol. 15, no. May, pp. 1–11, 2015.
[5] PN. Kiran and N. Saxena, “Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved,” International Journal of Hybrid Information Technology, vol.9,no.2,pp.111– 122,(2016).
[6] D. Nayak, “Power Efficient Design of a Novel SRAM Cell with Higher Write Ability,” IEEE Conference, pp. 2–7, 2015.
[7] Z. Liu , V. Kursun, “Characterization of a Novel Nine- Transistor SRAM Cell,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 4, pp. 488– 492, 2008.
[8] S. Patel and S. Pandey, “Analysis of 8T SRAM Cell Using Leakage Reduction Technique,” International Journal of Advanced Research in Computer Engineering & Technology (IJARCET), vol. 4, no. 12, pp. 4395–4399, 2015.
[9] O. R. Dasar, S. Narmada, T. Pramod, R. Belavadi, and H. P. Rajani, “Schmitt Trigger based Asymmetric SRAM in Submicron Technology,” ELSEVIER, pp. 256–265, 2013.
[10] A. Agal and B. Krishan, “6T SRAM Cell : Design And Analysis,” Journal of Engineering Research and Applications, vol. 4, no. 3, pp. 574–577, 2014.
[11] PN. Kiran and N. Saxena “Design and Analysis of Different Types SRAM Cell Topologies,” 2ND International Conference on Electronics and Communication System (ICECS) , pp. 1060–1065, 2015.
[12] P. Upadhyay, S. K. Chhotray, R. Kar, D. Mandal, and S. P. Ghoshal, “Analysis of Static Noise Margin and Power Dissipation of a Proposed Low Voltage Swing 8T SRAM cell,” IEEE Conference on Information and Communication Technologies, no. Ict, pp. 316–320, 2013.
[13] S. Mookerjea, D. Mohata and R. Krishnan,`` Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications``, IEEE Conference,pp.1-3,2009.

—Leakage current, power dissipation, Read stability, Read/ Write delay.