A drowsy cache method based 6T SRAM cell with different performance parameter at 32 nm Technology
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2016 by IJETT Journal|
|Year of Publication : 2016|
|Authors : Garima Upadhyay, Amit Singh Rajput, Nikhil Saxena
|DOI : 10.14445/22315381/IJETT-V42P271|
Garima Upadhyay, Amit Singh Rajput, Nikhil Saxena "A drowsy cache method based 6T SRAM cell with different performance parameter at 32 nm Technology", International Journal of Engineering Trends and Technology (IJETT), V42(8),411-415 December 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Now a day, speedy growth of portable or hardly applications are need of technology. These hardly applications bounded the static random access memory (SRAM) topologies to consider about low leakage current and reduce power consumption. To reduce leakage current and enhance stability many topologies proposed in conventional 6T SRAM cell. This paper presents a drowsy cache method in conventional 6T SRAM cell to boost cell performance at 0.9V power supply. In this paper, we propose a method to achieve 8x and 6x time enhancement in leakage current and power dissipation respectively compare to conventional 6T SRAM cell. Simulations results are improved in read stability read/ write delay, ION/IOFF, leakage current and power dissipation using 32 nm technologies.
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—Leakage current, power dissipation, Read stability, Read/ Write delay.