A Survey on Low-Power High Speed Full Adder Circuit in DSM Technology
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Hemraj Jijne, Ashish Raghuwanshi
|DOI : 10.14445/22315381/IJETT-V43P230|
Hemraj Jijne, Ashish Raghuwanshi "A Survey on Low-Power High Speed Full Adder Circuit in DSM Technology", International Journal of Engineering Trends and Technology (IJETT), V43(3),179-184 January 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Adders are one of the most basic building blocks in digital components present in the Arithmetic Logic Unit (ALU) .the performance of an adder have a significant impact on the overall performance of a digital system. The existing design is compared with some existing designs for power consumption, delay, PDP at various frequencies viz 10 MHz and 300 MHz. the simulations are carried out on HSPICE by using CMOS technology and the simulation results are analyzed to verify the superiority of the design over the existing designs. Maximum saving of power delay product is at low frequency of circuit is 96.8% with respect to C-CMOS and significant improvement is observed at other frequencies also. The power consumption increases at a slow rate in comparison to other adders with increase in frequency. In this paper we study about various adder circuit and find the merits and demerits of the adder circuit for further development of adder circuit which consume low power and area.
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(Size 10 & Bold) — Low power, GDI, SERF, Hybrid adder.