Implementation of Aging-Aware Multiplier Design for Area and Power Critical Applications
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : A.Prasanna Lakshmi, S. Prabhu Das
A.Prasanna Lakshmi, S. Prabhu Das "Implementation of Aging-Aware Multiplier Design for Area and Power Critical Applications", International Journal of Engineering Trends and Technology (IJETT), V44(2),85-90 February 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
The main constraint in VLSI system design is to achieve low power devices. In any digital filter, multipliers are the major elements. The throughput is the major parameter of multiplier that influences the performance of multiplier. For long term usage, aging becomes the main constraint that affects the performance of the system. Majorly aged systems fail due to delay problems. There are many approaches to design multipliers that reduce this aging effect. But these systems require large area, power. Moreover, timing violations occur when fixed latency designs are used. For reducing these timing violations and for implementing an aging reliable low power multiplier, adaptive hold logic is used. The transistor speeds are influenced by both negative and positive bias temperatures, for long term applications due to aging effect, the system may fail to perform because of timing violations. Therefore, it is necessary to implement the high performance designs. Here we propose a reversible Wallace Tree multiplier design with razor flip flop based multiplier circuit. This design is able to provide high throughput for area power critical applications. The proposed method can be digital filters to enhance the performance in the real time environment.
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The proposed method can be digital filters to enhance the performance in the real time environment.