Comparative Analysis of Low Power Adiabatic Logic Circuits in DSM Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-45 Number-3
Year of Publication : 2017
Authors : Shaefali Dixit, Ashish Raghuwanshi

Citation 

Shaefali Dixit, Ashish Raghuwanshi " Comparative Analysis of Low Power Adiabatic Logic Circuits in DSM Technology ", International Journal of Engineering Trends and Technology (IJETT), V45(3),98-102 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
With the continuous scaling down of technology, in the field of integrated circuit design, low power dissipation has become one of the primary focus of the research. With the increasing demand for low power devices adiabatic logic gates proves to be an effective solution. This paper investigates different adiabatic logic families such as ECRL, 2N-2N2P and PFAL. The main aim of this paper is to simulate various logic gates using conventional CMOS and different adiabatic logic families, and thus compare for the effectiveness in terms of lower power dissipation. All simulations are carried out using HSPICE at 65nm technology with supply voltage is 1V at 100MHz frequency, for fair comparison of results W/L ratio of all the circuit is same. Finally average power dissipation characteristics are plotted with the help of a graph and comparisons are made between different logic families.

 References

[1] Synopsys Inc. CCS Power Technical White Paper. Version 3.0, 2006
[2] Denker J S. A review of adiabatic computing. In: IEEE Symposium on Low Power Electronics, San Diego, 1994. 94–97
[3] Calhoun B H, Khanna S, Mann R, et al. Sub-threshold circuit design with shrinking CMOS devices. In: IEEE International Symposium on Circuits and Systems, Taipei, 2009. 2541–2544
[4] Hemantha S, Dhawan A, Haranath K. Multi-threshold CMOS design for low power digital circuits. In: 2008 IEEE Region 10 Conference on TENCON, Hyderabad, 2008. 1-5
[5] Y. Moon and D.K. Jeong, “An efficient charge recovery logic circuit,” IEEE Journal of Solid-State Circuits, Vol. 31, 1996, pp. 514-522 as accessed on October, 2014.
[6] A. Kramer, J.S. Denker et al.,” 2nd order adiabatic computing with 2N-2N and 2N-2N2P logic circuits,” Proc. Intern. Symp. Low Power Design, 1995, pp. 191-196 as accessed on September, 2014.
[7] A. Vetuli, S. Di Pascoli and L. M. Reyneri, “ Positive feedback in adiabatic logic,” Electronics Letters, Vol. 32, No. 20, Sep. 1996, pp. 1867 as accessed on July,2014.
[8] A. Blotti , S. Di Pascoli and R. Saletti, “Simple model for positive feedback adiabatic logic power consumption estimation,” Electronics Letters. Vol. 36, No. 2, Jan, 2000, pp. 116-118 as accessed on March, 2014.
[9] K. ROY and Y. YE,” Ultra Low Energy Computing using Adiabatic Switching Principle”, ECE Technical Reports, Purdue University, Indiana, as accessed on April, 2013.
[10] A. Chaudhary, M. Saha, M. Bhowmik et. al., "Implementation Of Circuit In Different Adiabatic Logic," IEEE Sponsored 2nd International Conference On Electronics And Communication System,ICECS, 2015.
[11] N. Liao, K. Liao et. al., “Low power adiabatic logic based on FinFETs”, Science China Information Sciences, Vol. 57, pp. 022402:1–022402:13, February 2014.
[12] Kramer A, Denker J S, Flower B, et al. 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits. In: Proceedings of the 1995 International Symposium on Low Power Design. New York: ACM, 1995. 191–196
[13] D. Shinghal, A. Saxena and A. Noor, “Adiabatic Logic Circuits: A retrospective,” MIT International Journal of Electronics and Communication Engineering, Vol. 3, No. 2, pp. 108–114, August 2013.

Keywords
Low power, CMOS, Adiabatic logic, ECRL, 2N-2N2P, PFAL, Power dissipation, Four phased power clock.