Implementation of High Performance Vedic Multiplier Based on Efficient carry select adder
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Anupama.k, Mrs.Lisa.c
|DOI : 10.14445/22315381/IJETT-V45P284|
Anupama.k, Mrs.Lisa.c "Implementation of High Performance Vedic Multiplier Based on Efficient carry select adder", International Journal of Engineering Trends and Technology (IJETT), V45(9),443-448 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In digital system multiplication is one of the most important function. Vedic maths, one of the ancient mathematics system make this tedious task much simple, efficient and suitable for VLSI implementation. This project implements high performance Vedic multiplier based on efficient square root carry select adder (SCSLA).The heart of a multiplier is adder.In this project the improvement is done on the adder to improve the total performance of the multiplier.In the existing system the first stage of SCSLA is RCA(ripple carry adder) with Cin=0 and second stage is BCE-1(Binary to excess one) converter.In moderrn digital systems parallel prefix adders(PPA) have been considered as the most efficient system for binary addition. Here,the first stage of the square root carry select adder is replaced by efficient and most common parallel prefix adders (PPA) such as Kogg stone adder(KSA),Brent-kung adder(BKA) and the hybrid of these two the Han Carlson adder (HCA). A comparative study is carried out to find out the efficient vedic multiplier with parallel prefix adder based SCLA .The result analysis shows that Vedic multiplier with HCA based squre root carry select adder exhibits efficient performance.The system is coded in Verilog HDL(hardware description language)and simulation,synthesis is carried out by using Model Sim 6.4a,Xilinx 14.5i.The implementation is done on Xilinx Spartan 3E FPGA(field programmable gate array).
 G.Challa Ram and Y.Rama Lakshmanna “Area Efficient
Modified Vedic Multiplier”,2016 International Conference on
Circuit, Power and Computing Technologies [ICCPCT].
 Mr. Ashish V. “Design of Han Carlson Adder for Implementation of CSLA” International Research Journal of Engineering and Technology (IRJET) , Proceedings of Sixth IRAJ International Conference, 6th October 2013.
 Vishwaja and Mahendran “Performance comparison of carry select adder with different techniques” International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE) ISSN: 0976-1353 Volume 20 Issue 2 – FEBRUARY 2016.
 Amita p. thakare and Saurabh agrawal, “32 bit carry select adder with bec-1 technique” Proceedings of Sixth IRAJ International Conference, 6th October 2013, Pune, India. ISBN: 978-93-82702-32-0
 R.Priya and J.Senthil Kumar “Implementation and Comparison of Vedic Multiplier using Area Efficient CSLA Architectures”, International Journal of Computer Applications (0975 – 8887) Volume 73– No.10, July 2013
 Gijin V George and Anoop Thomas “High Performance Vedic Multiplier Using Han-Carlson Adder” Department International Journal of Engineering Research & Technology (IJERT),ISSN: 2278-0181
 Megha Talsania and Eugene John, “A Comparative Analysis of Parallel Prefix Adders” Department of Electrical and Computer Engineering,University of Texas at San Antonio,San Antonio, TX 78249.
 Pappu P. Potdukhe, Vishal D. Jaiswal,” Review of carry select adder by using brent kung adder”,International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 4, Issue 10, October 2015
 Premananda B.S.and Samarth S. Pai” Design and Implementation of 8-Bit Vedic Multiplier” International Journal of Advanced Research in Electrical,Electronics and Instrumentation Engineering.
Brent-kung adder(BKA),Han-carlson adder(HCA),Kogg-stone adder(KSA), Parallel prefix adder(PPA), Ripple carry adder(RCA),Square root carry select adder(SCSLA), Vedic multiplier.