Variation of Power and Delay in Digital CMOS Circuit Design in DSM Technology
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Praveen Patel, Zahid Alam
Praveen Patel, Zahid Alam "Variation of Power and Delay in Digital CMOS Circuit Design in DSM Technology", International Journal of Engineering Trends and Technology (IJETT), V45(9),449-453 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In Deep Sub-Micron (DSM) technology, more number of gates are to be integrated on a single chip, so as to result in small geometries. But with this power densities and total power are rapidly increasing. Design of low power circuits has become important in a variety of application. However reducing power consumption involves a tradeoff between timing and area at different stages of the design. The successful power sensitive design requires engineers to accurately and efficiently be able to perform these tradeoffs. All the simulations are performed by using HSPICE tool at 45 and 32nm CMOS technology. We have compared Power, delay and PDP on conventional gates at low frequency at 250C and 1100C and analyze the impact of technology scaling with variation of temperature in all conventional gates.
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