Design and Analysis of Low Power High Speed 9T SRAM Design in Nanometer Regime

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2018 by IJETT Journal
Volume-55 Number-2
Year of Publication : 2018
Authors : Rahul Baghel, Suresh S Gawande
DOI :  10.14445/22315381/IJETT-V55P219

Citation 

Rahul Baghel, Suresh S Gawande "Design and Analysis of Low Power High Speed 9T SRAM Design in Nanometer Regime", International Journal of Engineering Trends and Technology (IJETT), V55(2),99-104 January 2018. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Nowadays low power SRAMs have become a critical component of many VLSI chips. This is especially true for microprocessors, where the demands of cache sizes chip are growing with each generation to abridge the increasing divergence in the speeds of the processors and the main memory. In the current scenario, power dissipation is performing an important role while designing integrated circuits and calculating their operating speeds, as well as low power dissipation is also requisite due to the high growth of battery operated applications. In this paper we have compared existing 4T, 6T, 7T, 8T and 9T SRAM cell with proposed 9T at 65nm and 45nm technology and analysed in terms power consumption, delay and PDP with supply voltage of 1V at 100MHz frequency.The proposed circuit reduces power consumption upto 34% when compared with other existing technique.

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Keywords
SNM, Power consumption, PDP