Implementation of Ultra Low Power Vlsi Design and Its Participation with Br4- Reversible Logics

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2020 by IJETT Journal
Volume-68 Issue-8
Year of Publication : 2020
Authors : G.R. Padmini, Rajesh Odela, P Sampath Kumar, K Saikumar
DOI :  10.14445/22315381/IJETT-V68I8P219S


MLA Style: G.R. Padmini, Rajesh Odela, P Sampath Kumar, K Saikumar  "Implementation of Ultra Low Power Vlsi Design and Its Participation with Br4- Reversible Logics" International Journal of Engineering Trends and Technology 68.8(2020):108-114. 

APA Style:G.R. Padmini, Rajesh Odela, P Sampath Kumar, K Saikumar. Implementation of Ultra Low Power Vlsi Design and Its Participation with Br4- Reversible Logics  International Journal of Engineering Trends and Technology, 68(8), 108-114.

In this research work an advanced ultralow power consumption circuit design approaches are defined. This method is more suitable for providing the support to modern technologies such as mobiles, PCs, tablets, laptops, super computers etc. In VLSI era size, memory, power back up, speed of operations are major necessary constraints. This foremost restrains related to present low power applications; these are mainly depending on VLSI chips. So, all discussed parameters are necessary to full fill for advanced designs. Moreover, economy is another more subject while design an ultra-low power SoC chips, therefore leakage power controlling, power maintenance schemes are overcome the limitations. Moreover, the major issue related to VLSI technology is cost and speed of operations. For ultra-low power technology leakage currents assumed to be reduced, otherwise circuits consume more power. In this research work novel leakage reduction-based chip designs are proposed through reversible logic gates. These proposed systems achieve 20% power saving, 98.7% accuracy and 20% speed of operations improved compared to existed methods.


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Low power, Power Organization, reversible logic gates, speed of operations.