Enhanced MAC Controller Design for 2D Convolution Image Processing on FPGA

Enhanced MAC Controller Design for 2D Convolution Image Processing on FPGA

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2021 by IJETT Journal
Volume-69 Issue-9
Year of Publication : 2021
Authors : Chiranjeevi G N, Dr Subhash Kulkarni
DOI :  10.14445/22315381/IJETT-V69I9P207

How to Cite?

Chiranjeevi G N, Dr Subhash Kulkarni, "Enhanced MAC Controller Design for 2D Convolution Image Processing on FPGA," International Journal of Engineering Trends and Technology, vol. 69, no. 9, pp. 51-55, 2021. Crossref, https://doi.org/10.14445/22315381/IJETT-V69I9P207

Majorities of image processing algorithms are two-dimensional (2D) and localized by their very nature. As a result, the 2D convolution function has significant implications for the requirements involving image processing. 2D Convolution and MAC design is the process used to do a variety of image analysis tasks, including picture blurring, softening, feature extraction, and image classification. The major purpose of this study is to create a more efficient MAC control block-based architecture for 2D convolution. This 2D algorithm can be implemented in hardware with a smaller number of modules, multipliers, adders, and control blocks, resulting in substantial hardware savings and reduced LUTs. Simulations were carried out in Verilog and developed and tested using Xilinx Vertex family Field Programmable Gate Arrays (FPGA) technology. In comparison to the conventional 2D convolution implementation, the recommended 2D convolution architectural technique is substantially faster and requires much fewer hardware resources.

Xilinx Vertex, 2D convolution, MAC, Image processing FPGA, Image enhancement, vertex, and Zynq7000 SOC

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