FPGA Implementation Of VM-CSA Fir Filter With Reduced Area And Delay Using Optimal Designs

FPGA Implementation Of VM-CSA Fir Filter With Reduced Area And Delay Using Optimal Designs

© 2021 by IJETT Journal
Volume-69 Issue-9
Year of Publication : 2021
Authors : Arunjyothi Eddla, Dr.VY.Jayasree Pappu
DOI :  10.14445/22315381/IJETT-V69I9P224

How to Cite?

Arunjyothi Eddla, Dr.VY.Jayasree Pappu, "FPGA Implementation Of VM-CSA Fir Filter With Reduced Area And Delay Using Optimal Designs," International Journal of Engineering Trends and Technology, vol. 69, no. 9, pp. 203-211, 2021. Crossref, https://doi.org/10.14445/22315381/IJETT-V69I9P224

Because of its various properties, such as Bounded-Input-Bounded-Output (BIBO) stability, phase linearity, and ease of implementation, the Finite Impulse Response (FIR) filter is widely employed in digital signal processing applications. High-order filters, on the other hand, need a large number of multipliers. As the number of multipliers grows, the hardware complexity and power of the FIR filter grows as well. In digital signal processing applications, the design of the low area and low power FIR filters is critical. To reduce hardware consumption, an essential form of FIR filter called the Interpolated Spectral Parameter Approximation (ISPA) filter is introduced in this study. To reduce the number of logical components in the ISPA filter, the Carry SKIP Adder (CSA) and Vedic Multiplier (VM) are combined. Furthermore, raising the ISPA filter`s working frequency reduces the ISPA filter`s latency. The Parks-McClellan algorithm will be used to create the coefficient. The ISPA filter, as well as the optimum adder and multiplier, are implemented using Modelsim 10.5 and Xilinx 14.4. The suggested ISPA filter`s performance is evaluated in terms of filter output, LUT, flip flops, slices, power, and delay.

Carry Look Ahead adder, Finite Impulse Response, Interpolated Spectral Parameter Approximation, Parks-McClellan, and Vedic Multiplier

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