A Novel NCL Threshold Gate Implementation for Low Power Asynchronous Designs using FinFETs

A Novel NCL Threshold Gate Implementation for Low Power Asynchronous Designs using FinFETs

© 2022 by IJETT Journal
Volume-70 Issue-5
Year of Publication : 2022
Authors : Jayesh Diwan , Nagendra P. Gajjar
DOI :  10.14445/22315381/IJETT-V70I5P232

How to Cite?

Jayesh Diwan , Nagendra P. Gajjar, "A Novel NCL Threshold Gate Implementation for Low Power Asynchronous Designs using FinFETs," International Journal of Engineering Trends and Technology, vol. 70, no. 5, pp. 299-305, 2022. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I5P232

Recent advancement in CMOS-based synchronous designs suffers from the unmanageable clock and power related issues. Beyond 22nm technology, CMOS devices exhibit poor short channel control and unreliable performance. However, the FinFET device is a reliable alternative for CMOS at a deep submicron scale, offering better gate control, lower short channel effects, and excellent electrostatics. In contrast to the Synchronous design style, the Null Convention Logic based asynchronous design paradigm offers faster operating speed, comparable power efficiency, and reduced EMI, with a modular design approach in complex systems (SoCs). This paper presents an implementation of CMOS and FinFET-based NCL threshold gates in 16nm technology. The proposed research demonstrates an average 21% power improvement and an average 33% speed improvement for FinFET-based NCL threshold gates over their CMOS counterpart. Also, the proposed NCL gate structure exhibits a 16.5% improvement in speed compared to its semi-static variant and an average 7.2% power improvement compared to its static variant.

FinFETs, Null Convention Logic, Multi-rail Logic, Quasi Delay-Insensitive circuits, Self-timed Design.

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