Citation :

Srividya B V, Nagarathna, Soumya S, Harikeerthan M K, "Fast and Low Power Implementation of RSA on Ternary Galois Field," International Journal of Engineering Trends and Technology (IJETT), vol. 73, no. 12, pp. 10-23, 2025. Crossref, https://doi.org/10.14445/22315381/IJETT-V73I12P102

Abstract

Data transmission and reception are getting more expensive. As a result, it is now more challenging to store and maintain the security of information. This necessitates a secure connection in each application. One potential method for data security is cryptography. Besides defense-related uses, cryptography has many other uses in the modern world, including social networking, email, and e-commerce. Cryptography is a crucial element of pre-designed interfaces, such as embedded systems. The majority of cryptographic methods involve modular operations involving Galois Fields GF (pm), where ‘m’ stands for power and ‘p’ for base, which are prime numbers. This research uses the Forced Stack approach, which has a low leakage power, to implement the Ternary Galois field. This work reports a low-power and high-frequency RSA cryptosystem to accomplish the goal. In order to implement the algorithm in hardware, Ternary circuits that are capable of efficiently carrying out the encryption, decryption, key generation, and key storage operations for the RSA algorithm have been designed using Cadence Virtuoso.

Keywords

Low power ternary VLSI circuits, Ternary galois field, RSA algorithm, Encryption, Decryption.

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