International Journal of Engineering
Trends and Technology

Research Article | Open Access | Download PDF
Volume 74 | Issue 10 | Year 2026 | Article Id. IJETT-V74I10P137 | DOI : https://doi.org/10.14445/22315381/IJETT-V74I10P137

A Hybrid Analytical-Machine Learning Framework for Performance and Energy Modelling of CPU-FPGA Heterogeneous Architectures

Sabbar Hadi Salh, Maher Shahatha Mahmood, Methaq Kadhum Hussain, Nooraldeen R. Hamza

Received Revised Accepted Published
19 May 2026 10 Sep 2026 16 Sep 2026 27 Oct 2026

Citation :

Sabbar Hadi Salh, Maher Shahatha Mahmood, Methaq Kadhum Hussain, Nooraldeen R. Hamza, "A Hybrid Analytical-Machine Learning Framework for Performance and Energy Modelling of CPU-FPGA Heterogeneous Architectures," International Journal of Engineering Trends and Technology (IJETT), vol. 74, no. 10, pp. 530-546, 2026. Crossref, https://doi.org/10.14445/22315381/IJETT-V74I10P137

Abstract

Modern data centres increasingly employ heterogeneous computing platforms that combine Field-Programmable Gate Arrays (FPGAs) with general-purpose processors to improve performance and energy efficiency. The effectiveness of these platforms depends strongly on the level of coupling between the host CPU and the reconfigurable fabric. Existing approaches for evaluating CPU-FPGA systems often involve a trade-off between simplified analytical models and computationally expensive detailed simulations, limiting their suitability for large-scale early design-space exploration. This paper presents a hybrid analytical-machine-learning framework for performance and energy modelling of CPU-FPGA heterogeneous architectures. The framework introduces a workload-adaptive overlap function γ(N) and a bus-contention factor κ to represent workload-dependent communication-computation overlap and communication contention. A dual-state energy model accounts for the active and idle power of both the CPU and FPGA. A Gradient-Boosted-Tree (GBT) surrogate, trained on samples generated by the analytical model, provides computationally efficient repeated evaluations for large-scale design-space exploration. An Adaptive Coupling Selector (ACS) further supports architecture selection by considering Energy-Delay Product (EDP) and normalized deployment cost in the (N,w E ) decision space. The framework evaluates three representative coupling topologies: External (EXT), Shared-Memory (SHM), and on-die Coprocessor (COP). Comparison with five published FPGA benchmarks yields Mean Absolute Percentage Errors (MAPE) of 4.4% for speed-up and 7.0% for total energy. At a representative workload of N=10 8 operations, COP achieves a speed-up of 1.20× over the CPU-only baseline, compared with 0.39× for EXT, while reducing total energy consumption by approximately 57.7% relative to EXT under the evaluated baseline parameters. A 5,000-trial Monte-Carlo analysis further indicates that the relative performance and energy trends remain stable under the considered parameter perturbations. Overall, the framework provides a computationally efficient approach for early exploration of CPU-FPGA coupling alternatives under performance, energy, and deployment-cost considerations.

Keywords

CPU-FPGA heterogeneous computing, Coupling architectures, Energy efficiency, Machine-Learning surrogate, Design-Space exploration.

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